Datasheet ADG733, ADG734 (Analog Devices) - 6

FabricanteAnalog Devices
DescripciónCMOS, 2.5 Ω Low Voltage, Triple/Quad SPDT Switches
Páginas / Página12 / 6 — ADG733/ADG734. Table I. ADG733 Truth Table. Table II. ADG734 Truth Table. …
RevisiónB
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Idioma del documentoInglés

ADG733/ADG734. Table I. ADG733 Truth Table. Table II. ADG734 Truth Table. ON Switch. Logic. Switch A. Switch B. TERMINOLOGY

ADG733/ADG734 Table I ADG733 Truth Table Table II ADG734 Truth Table ON Switch Logic Switch A Switch B TERMINOLOGY

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ADG733/ADG734 Table I. ADG733 Truth Table Table II. ADG734 Truth Table A2 A1 A0 EN ON Switch Logic Switch A Switch B
X X X 1 None 0 OFF ON 0 0 0 0 D1-S1A, D2-S2A, D3-S3A 1 ON OFF 0 0 1 0 D1-S1B, D2-S2A, D3-S3A 0 1 0 0 D1-S1A, D2-S2B, D3-S3A 0 1 1 0 D1-S1B, D2-S2B, D3-S3A 1 0 0 0 D1-S1A, D2-S2A, D3-S3B 1 0 1 0 D1-S1B, D2-S2A, D3-S3B 1 1 0 0 D1-S1A, D2-S2B, D3-S3B 1 1 1 0 D1-S1B, D2-S2B, D3-S3B X = Don’t Care.
TERMINOLOGY
VDD Most Positive Power Supply Potential VSS Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to ground close to the device. IDD Positive Supply Current ISS Negative Supply Current GND Ground (0 V) Reference S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. AX Logic Control Input EN Active low device enable VD (VS) Analog Voltage on Terminals D and S RON Ohmic Resistance between D and S ∆RON On Resistance Match between any Two Channels (i.e., RONmax and RONmin) RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (OFF) Source Leakage Current with the Switch “OFF” ID, IS (ON) Channel Leakage Current with the Switch “ON” VINL Maximum Input Voltage for Logic “0” VINH Minimum Input Voltage for Logic “1” IINL(IINH) Input Current of the Digital Input CS (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. CD, CS(ON) “ON” Switch Capacitance. Measured with reference to ground. CIN Digital Input Capacitance tON Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition tOFF Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition tON(EN) Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition tOFF(EN) Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition tOPEN “OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to Another Charge A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching Off Isolation A Measure of Unwanted Signal Coupling through an “OFF” Switch. Crosstalk A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Para- sitic Capacitance On Response The Frequency Response of the “ON” Switch Insertion Loss The Loss Due to the On Resistance of the switch –6– REV. B Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Specifications Absolute Maximum Ratings Pin Configurations Terminology Typical Performance Characteristics Test Circuits Outline Dimensions Ordering Guide Revision History