Datasheet PIC16F17126, PIC16F17146 (Microchip) - 9

PIC16F17126/46 Packages 1. Packages Table 1-1. Packages 16-Pin 20-Pin 14-Pin 14-Pin 14-Pin 20-Pin 20-Pin 20-Pin Device VQFN VQFN PDIP SOIC TSSOP PDIP SOIC SSOP 4x4x1 4x4x1
PIC16F17126 • • • • PIC16F17146 • • • • © 2021-2022 Microchip Technology Inc.
Preliminary Datasheet
DS40002343C-page 9 and its subsidiaries Document Outline Introduction PIC16F171 Family Summary Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Block Diagram Table of Contents 1.  Packages 2.  Pin Diagrams 3.  Pin Allocation Tables 4.  Guidelines for Getting Started with PIC16F171 Microcontrollers 4.1.  Basic Connection Requirements 4.2.  Power Supply Pins 4.2.1.  Decoupling Capacitors 4.2.2.  Tank Capacitors 4.3.  Master Clear (MCLR) Pin 4.4.  In-Circuit Serial Programming™ (ICSP™) Pins 4.5.  Unused I/Os 5.  Register and Bit Naming Conventions 5.1.  Register Names 5.2.  Bit Names 5.2.1.  Short Bit Names 5.2.2.  Long Bit Names 5.2.3.  Bit Fields 5.3.  Register and Bit Naming Exceptions 5.3.1.  Status, Interrupt and Mirror Bits 6.  Register Legend 7.  Enhanced Mid-Range CPU 7.1.  Automatic Interrupt Context Saving 7.2.  16-Level Stack with Overflow and Underflow 7.3.  File Select Registers 7.4.  Instruction Set 8.  Device Configuration 8.1.  Configuration Words 8.2.  Code Protection 8.3.  Write Protection 8.4.  User ID 8.5.  Device ID and Revision ID 8.6.  Register Definitions: Configuration Settings 8.6.1.  CONFIG1 8.6.2.  CONFIG2 8.6.3.  CONFIG3 8.6.4.  CONFIG4 8.6.5.  CONFIG5 8.7.  Register Definitions: Device ID and Revision ID 8.7.1.  Device ID 8.7.2.  Revision ID 9.  Memory Organization 9.1.  Program Memory Organization 9.1.1.  Reading Program Memory as Data 9.1.1.1.  RETLW Instruction 9.1.1.2.  Indirect Read with FSR 9.1.2.  Memory Access Partition (MAP) 9.1.2.1.  Application Block 9.1.2.2.  Boot Block 9.1.2.3.  Storage Area Flash 9.1.2.4.  Memory Write Protection 9.1.2.5.  Memory Violation 9.1.3.  Device Information Area (DIA) 9.1.3.1.  Microchip Unique Identifier (MUI) 9.1.3.2.  External Unique Identifier (EUI) 9.1.3.3.  Standard Parameters for the Temperature Sensor 9.1.3.4.  Fixed Voltage Reference Data 9.1.4.  Device Configuration Information (DCI) 9.1.4.1.  DIA and DCI Access 9.2.  Data Memory Organization 9.2.1.  Bank Selection 9.2.2.  Core Registers 9.2.3.  Special Function Register 9.2.4.  General Purpose RAM 9.2.5.  Common RAM 9.2.6.  Device Memory Maps 9.3.  STATUS Register 9.4.  PCL and PCLATH 9.4.1.  Modifying PCL 9.4.2.  Computed GOTO 9.4.3.  Computed Function Calls 9.4.4.  Branching 9.5.  Stack 9.5.1.  Accessing the Stack 9.5.2.  Overflow/Underflow Reset 9.6.  Indirect Addressing 9.6.1.  Traditional/Banked Data Memory 9.6.2.  Linear Data Memory 9.6.3.  Program Flash Memory 9.6.4.  Data EEPROM Memory 9.7.  Register Definitions: Memory Organization 9.7.1.  INDF0 9.7.2.  INDF1 9.7.3.  PCL 9.7.4.  STATUS 9.7.5.  FSR0 9.7.6.  FSR1 9.7.7.  BSR 9.7.8.  WREG 9.7.9.  PCLATH 9.8.  Register Summary - Memory Organization 10.  Resets 10.1.  Power-on Reset (POR) 10.1.1.  Programming Mode Exit 10.2.  Brown-out Reset (BOR) 10.2.1.  BOR Is Always On 10.2.2.  BOR Is Off in Sleep 10.2.3.  BOR Controlled by Software 10.2.4.  BOR Is Always Off 10.3.  MCLR Reset 10.3.1.  MCLR Enabled 10.3.2.  MCLR Disabled 10.4.  Watchdog Timer (WDT) Reset 10.5.  RESET Instruction 10.6.  Stack Overflow/Underflow Reset 10.7.  Power-Up Timer (PWRT) 10.8.  Start-Up Sequence 10.9.  Memory Execution Violation 10.10.  Determining the Cause of a Reset 10.11.  Power Control (PCONx) Register 10.12.  Register Definitions: Power Control 10.12.1.  BORCON 10.12.2.  PCON0 10.12.3.  PCON1 10.13.  Register Summary - Power Control 11.  OSC - Oscillator Module (With Fail-Safe Clock Monitor) 11.1.  Clock Source Types 11.1.1.  External Clock Sources 11.1.1.1.  EC Mode 11.1.1.2.  LP, XT, HS Modes 11.1.1.3.  Oscillator Start-Up Timer (OST) 11.1.1.4.  4x PLL 11.1.1.5.  Secondary Oscillator 11.1.1.5.1.  SOSC Start-Up Timing 11.1.2.  Internal Clock Sources 11.1.2.1.  HFINTOSC 11.1.2.1.1.  HFINTOSC Frequency Tuning 11.1.2.2.  MFINTOSC 11.1.2.3.  SFINTOSC 11.1.2.4.  LFINTOSC 11.1.2.5.  ADCRC 11.1.3.  Oscillator Status and Manual Enable 11.2.  Clock Switching 11.2.1.  NOSC and NDIV Bits 11.2.2.  COSC and CDIV Bits 11.2.3.  CSWHOLD 11.2.4.  PLL Input Switch 11.2.5.  Clock Switch and Sleep 11.3.  Fail-Safe Clock Monitor (FSCM) 11.3.1.  Fail-Safe Detection 11.3.2.  Fail-Safe Operation 11.3.3.  Fail-Safe Condition Clearing 11.3.4.  Reset or Wake-Up from Sleep 11.4.  Active Clock Tuning (ACT) 11.4.1.  ACT Lock Status 11.4.2.  ACT Out-of-Range Status 11.4.3.  ACT Update Disable 11.4.4.  ACT Interrupts 11.5.  Register Definitions: Oscillator Module 11.5.1.  ACTCON 11.5.2.  OSCCON1 11.5.3.  OSCCON2 11.5.4.  OSCCON3 11.5.5.  OSCTUNE 11.5.6.  OSCFRQ 11.5.7.  OSCSTAT 11.5.8.  OSCEN 11.6.  Register Summary - Oscillator Module 12.  INT - Interrupts 12.1.  Overview 12.2.  INTCON Register 12.3.  PIE Registers 12.4.  PIR Registers 12.5.  Operation 12.6.  Interrupt Latency 12.7.  Interrupts During Sleep 12.8.  INT Pin 12.9.  Automatic Context Saving 12.10.  Register Definitions: Interrupt Control 12.10.1.  INTCON 12.10.2.  PIE0 12.10.3.  PIE1 12.10.4.  PIE2 12.10.5.  PIE3 12.10.6.  PIE4 12.10.7.  PIE5 12.10.8.  PIE6 12.10.9.  PIR0 12.10.10.  PIR1 12.10.11.  PIR2 12.10.12.  PIR3 12.10.13.  PIR4 12.10.14.  PIR5 12.10.15.  PIR6 12.11.  Register Summary - Interrupt Control 13.  Power-Saving Modes 13.1.  Doze Mode 13.1.1.  Doze Operation 13.1.2.  Interrupts During Doze 13.2.  Sleep Mode 13.2.1.  Wake-Up from Sleep 13.2.2.  Wake-Up Using Interrupts 13.3.  Idle Mode 13.3.1.  Idle and Interrupts 13.3.2.  Idle and WWDT 13.4.  Peripheral Operation in Power-Saving Modes 13.5.  Register Definitions: Power-Savings Control 13.5.1.  CPUDOZE 13.6.  Register Summary - Power-Savings Control 14.  WWDT - Windowed Watchdog Timer 14.1.  Independent Clock Source 14.2.  WWDT Operating Modes 14.2.1.  WWDT Is Always On 14.2.2.  WWDT Is Off in Sleep 14.2.3.  WWDT Controlled by Software 14.3.  Time-Out Period 14.4.  Watchdog Window 14.5.  Clearing the Watchdog Timer 14.5.1.  CLRWDT Considerations (Windowed Mode) 14.6.  Operation During Sleep 14.7.  Register Definitions: Windowed Watchdog Timer Control 14.7.1.  WDTCON0 14.7.2.  WDTCON1 14.7.3.  WDTPSH 14.7.4.  WDTPSL 14.7.5.  WDTTMR 14.8.  Register Summary - WDT Control 15.  NVM - Nonvolatile Memory Control 15.1.  Program Flash Memory (PFM) 15.1.1.  FSR and INDF Access 15.1.1.1.  FSR Read 15.1.1.2.  FSR Write 15.1.2.  NVMREG Access 15.1.2.1.  NVMREG Read Operation 15.1.2.2.  NVM Unlock Sequence 15.1.2.3.  NVMREG Erase of Program Memory 15.1.2.4.  NVMREG Write to Program Memory 15.1.2.5.  Modifying Flash Program Memory 15.1.2.6.  NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID, and Configuration Words 15.1.2.7.  Write Verify 15.1.2.8.  WRERR Bit 15.2.  Data Flash Memory (DFM) 15.2.1.  FSR and INDF Access 15.2.1.1.  FSR DFM Read 15.2.1.2.  FSR DFM Write 15.2.2.  NVMREG Access 15.2.2.1.  NVMREG Read Operation 15.2.2.2.  NVM Unlock Sequence 15.2.2.3.  NVMREG Erase of DFM 15.2.2.4.  NVMREG Write to DFM 15.2.2.5.  WRERR Bit 15.3.  Register Definitions: Nonvolatile Memory Control 15.3.1.  NVMADR 15.3.2.  NVMDAT 15.3.3.  NVMCON1 15.3.4.  NVMCON2 15.4.  Register Summary - NVM Control 16.  I/O Ports 16.1.  Overview 16.2.  PORTx - Data Register 16.3.  LATx - Output Latch 16.4.  TRISx - Direction Control 16.5.  ANSELx - Analog Control 16.6.  WPUx - Weak Pull-Up Control 16.7.  INLVLx - Input Threshold Control 16.8.  SLRCONx - Slew Rate Control 16.9.  ODCONx - Open-Drain Control 16.10.  Edge Selectable Interrupt-on-Change 16.11.  I2C Pad Control 16.12.  I/O Priorities 16.13.  MCLR/VPP/RA3 Pin 16.14.  Register Definitions: Port Control 16.14.1.  PORTx 16.14.2.  LATx 16.14.3.  TRISx 16.14.4.  ANSELx 16.14.5.  WPUx 16.14.6.  INLVLx 16.14.7.  SLRCONx 16.14.8.  ODCONx 16.14.9.  RxyI2C 16.15.  Register Summary - IO Ports 17.  IOC - Interrupt-on-Change 17.1.  Overview 17.2.  Enabling the Module 17.3.  Individual Pin Configuration 17.4.  Interrupt Flags 17.5.  Clearing Interrupt Flags 17.6.  Operation in Sleep 17.7.  Register Definitions: Interrupt-on-Change Control 17.7.1.  IOCxF 17.7.2.  IOCxN 17.7.3.  IOCxP 17.8.  Register Summary - Interrupt-on-Change 18.  PPS - Peripheral Pin Select Module 18.1.  Overview 18.2.  PPS Inputs 18.3.  PPS Outputs 18.4.  Bidirectional Pins 18.5.  PPS Lock 18.5.1.  PPS One-Way Lock 18.6.  Operation During Sleep 18.7.  Effects of a Reset 18.8.  Register Definitions: Peripheral Pin Select (PPS) 18.8.1.  xxxPPS 18.8.2.  RxyPPS 18.8.3.  PPSLOCK 18.9.  Register Summary - Peripheral Pin Select Module 19.  CRC - Cyclic Redundancy Check Module with Memory Scanner 19.1.  Module Overview 19.2.  Polynomial Implementation 19.3.  Data Sources 19.3.1.  CRC from User Data 19.3.2.  CRC from Flash 19.4.  CRC Check Value 19.5.  CRC Interrupt 19.6.  Configuring the CRC Module 19.6.1.  Register Overlay 19.7.  Scanner Module Overview 19.8.  Scanning Modes 19.8.1.  Concurrent Mode 19.8.2.  Burst Mode 19.8.3.  Peek Mode 19.8.4.  Triggered Mode 19.9.  Configuring the Scanner 19.10.  Scanner Interrupts 19.10.1.  Operation During Interrupts 19.11.  WWDT Interaction 19.12.  Operation During Sleep 19.13.  Peripheral Module Disable 19.14.  Register Definitions: CRC and Scanner Control 19.14.1.  CRCCON0 19.14.2.  CRCCON1 19.14.3.  CRCCON2 19.14.4.  CRCDATA 19.14.5.  CRCOUT 19.14.6.  CRCSHIFT 19.14.7.  CRCXOR 19.14.8.  SCANCON0 19.14.9.  SCANLADR 19.14.10.  SCANHADR 19.14.11.  SCANTRIG 19.15.  Register Summary - CRC 20.  PMD - Peripheral Module Disable 20.1.  Overview 20.2.  Disabling a Module 20.3.  Enabling a Module 20.4.  Register Definitions: Peripheral Module Disable 20.4.1.  PMD0 20.4.2.  PMD1 20.4.3.  PMD2 20.4.4.  PMD3 20.4.5.  PMD4 20.5.  Register Summary - PMD 21.  CLKREF - Reference Clock Output Module 21.1.  Clock Source 21.1.1.  Clock Synchronization 21.2.  Programmable Clock Divider 21.3.  Selectable Duty Cycle 21.4.  Operation in Sleep Mode 21.5.  Register Definitions: Reference Clock 21.5.1.  CLKRCON 21.5.2.  CLKRCLK 21.6.  Register Summary - Reference CLK 22.  TMR0 - Timer0 Module 22.1.  Timer0 Operation 22.1.1.  8-Bit Mode 22.1.2.  16-Bit Mode 22.2.  Clock Selection 22.2.1.  Synchronous Mode 22.2.2.  Asynchronous Mode 22.2.3.  Programmable Prescaler 22.2.4.  Programmable Postscaler 22.3.  Timer0 Output and Interrupt 22.3.1.  Timer0 Output 22.3.2.  Timer0 Interrupt 22.3.3.  Timer0 Example 22.4.  Operation During Sleep 22.5.  Register Definitions: Timer0 Control 22.5.1.  T0CON0 22.5.2.  T0CON1 22.5.3.  TMR0H 22.5.4.  TMR0L 22.6.  Register Summary - Timer0 23.  TMR1 - Timer1 Module with Gate Control 23.1.  Timer1 Operation 23.2.  Clock Source Selection 23.2.1.  Internal Clock Source 23.2.2.  External Clock Source 23.3.  Timer1 Prescaler 23.4.  Secondary Oscillator 23.5.  Timer1 Operation in Asynchronous Counter Mode 23.5.1.  Reading and Writing TMRx in Asynchronous Counter Mode 23.6.  Timer1 16-Bit Read/Write Mode 23.7.  Timer1 Gate 23.7.1.  Timer1 Gate Enable 23.7.2.  Timer1 Gate Source Selection 23.7.3.  Timer1 Gate Toggle Mode 23.7.4.  Timer1 Gate Single Pulse Mode 23.7.5.  Timer1 Gate Value Status 23.7.6.  Timer1 Gate Event Interrupt 23.8.  Timer1 Interrupt 23.9.  Timer1 Operation During Sleep 23.10.  CCP Capture/Compare Time Base 23.11.  CCP Special Event Trigger 23.12.  Peripheral Module Disable 23.13.  Register Definitions: Timer1 Control 23.13.1.  TxCON 23.13.2.  TxGCON 23.13.3.  TxCLK 23.13.4.  TxGATE 23.13.5.  TMRx 23.14.  Register Summary - Timer1 24.  TMR2 - Timer2 Module 24.1.  Timer2 Operation 24.1.1.  Free-Running Period Mode 24.1.2.  One Shot Mode 24.1.3.  Monostable Mode 24.2.  Timer2 Output 24.3.  External Reset Sources 24.4.  Timer2 Interrupt 24.5.  PSYNC Bit 24.6.  CSYNC Bit 24.7.  Operating Modes 24.8.  Operation Examples 24.8.1.  Software Gate Mode 24.8.2.  Hardware Gate Mode 24.8.3.  Edge Triggered Hardware Limit Mode 24.8.4.  Level Triggered Hardware Limit Mode 24.8.5.  Software Start One Shot Mode 24.8.6.  Edge Triggered One Shot Mode 24.8.7.  Edge Triggered Hardware Limit One Shot Mode 24.8.8.  Level Reset, Edge Triggered Hardware Limit One Shot Modes 24.8.9.  Edge Triggered Monostable Modes 24.8.10.  Level Triggered Hardware Limit One Shot Modes 24.9.  Timer2 Operation During Sleep 24.10.  Register Definitions: Timer2 Control 24.10.1.  TxTMR 24.10.2.  TxPR 24.10.3.  TxCON 24.10.4.  TxHLT 24.10.5.  TxCLKCON 24.10.6.  TxRST 24.11.  Register Summary - Timer2 25.  NCO - Numerically Controlled Oscillator Module 25.1.  NCO Operation 25.1.1.  NCO Clock Sources 25.1.2.  Accumulator 25.1.3.  Adder 25.1.4.  Increment Registers 25.2.  Fixed Duty Cycle Mode 25.3.  Pulse Frequency Mode 25.4.  Output Polarity Control 25.5.  Interrupts 25.6.  Effects of a Reset 25.7.  Operation in Sleep 25.8.  Register Definitions: NCO 25.8.1.  NCOxCON 25.8.2.  NCOxCLK 25.8.3.  NCOxACC 25.8.4.  NCOxINC 25.9.  Register Summary - NCO 26.  CWG - Complementary Waveform Generator Module 26.1.  Fundamental Operation 26.2.  Operating Modes 26.2.1.  Half Bridge Mode 26.2.2.  Push-Pull Mode 26.2.3.  Full Bridge Mode 26.2.3.1.  Direction Change in Full Bridge Mode 26.2.3.2.  Dead-Band Delay in Full Bridge Mode 26.2.4.  Steering Modes 26.2.4.1.  Synchronous Steering Mode 26.2.4.2.  Asynchronous Steering Mode 26.2.4.3.  Start-Up Considerations 26.3.  Clock Source 26.4.  Selectable Input Sources 26.5.  Output Control 26.5.1.  CWG Output 26.5.2.  Polarity Control 26.6.  Dead-Band Control 26.6.1.  Dead-Band Functionality in Half Bridge Mode 26.6.2.  Dead-Band Functionality in Full Bridge Mode 26.7.  Rising Edge and Reverse Dead Band 26.8.  Falling Edge and Forward Dead Band 26.9.  Dead-Band Jitter 26.10.  Auto-Shutdown 26.10.1.  Shutdown 26.10.2.  Software Generated Shutdown 26.10.3.  External Input Source 26.10.4.  Pin Override Levels 26.10.5.  Auto-Shutdown Interrupts 26.11.  Auto-Shutdown Restart 26.11.1.  Software-Controlled Restart 26.11.2.  Auto-Restart 26.12.  Operation During Sleep 26.13.  Configuring the CWG 26.14.  Register Definitions: CWG Control 26.14.1.  CWGxCON0 26.14.2.  CWGxCON1 26.14.3.  CWGxCLK 26.14.4.  CWGxISM 26.14.5.  CWGxSTR 26.14.6.  CWGxAS0 26.14.7.  CWGxAS1 26.14.8.  CWGxDBR 26.14.9.  CWGxDBF 26.15.  Register Summary - CWG 27.  CCP - Capture/Compare/PWM Module 27.1.  CCP Module Configuration 27.1.1.  CCP Modules and Timer Resources 27.1.2.  Open-Drain Output Option 27.2.  Capture Mode 27.2.1.  Capture Sources 27.2.2.  Timer1 Mode for Capture 27.2.3.  Software Interrupt Mode 27.2.4.  CCP Prescaler 27.2.5.  Capture During Sleep 27.3.  Compare Mode 27.3.1.  CCPx Pin Configuration 27.3.2.  Timer1 Mode for Compare 27.3.3.  Compare During Sleep 27.4.  PWM Overview 27.4.1.  Standard PWM Operation 27.4.2.  Setup for PWM Operation 27.4.3.  Timer2 Timer Resource 27.4.4.  PWM Period 27.4.5.  PWM Duty Cycle 27.4.6.  PWM Resolution 27.4.7.  Operation in Sleep Mode 27.4.8.  Changes in System Clock Frequency 27.4.9.  Effects of Reset 27.5.  Register Definitions: CCP Control 27.5.1.  CCPxCON 27.5.2.  CCPxCAP 27.5.3.  CCPRx 27.6.  Register Summary - CCP Control 28.  Capture, Compare, and PWM Timers Selection 28.1.  Register Definitions: Capture, Compare, and PWM Timers Selection 28.1.1.  CCPTMRS0 28.2.  Register Summary - Capture, Compare, and PWM Timers Selection 29.  PWM - Pulse-Width Modulator with Compare 29.1.  Output Slices 29.1.1.  Output Polarity 29.1.2.  Operating Modes 29.1.2.1.  Left Aligned Mode 29.1.2.2.  Right Aligned Mode 29.1.2.3.  Center-Aligned Mode 29.1.2.4.  Variable Alignment Mode 29.1.2.5.  Compare Modes 29.1.2.5.1.  Pulsed Compare Mode 29.1.2.5.2.  Toggled Compare 29.1.3.  Push-Pull Mode 29.2.  Period Timer 29.3.  Clock Sources 29.3.1.  Clock Prescaler 29.4.  External Period Resets 29.5.  Buffered Period and Parameter Registers 29.6.  Synchronizing Multiple PWMs 29.7.  Interrupts 29.7.1.  Period Interrupt 29.7.1.1.  Period Interrupt Postscaler 29.7.2.  Parameter Interrupts 29.8.  Operation During Sleep 29.9.  Register Definitions: PWM Control 29.9.1.  PWMxERS 29.9.2.  PWMxCLK 29.9.3.  PWMxLDS 29.9.4.  PWMxPR 29.9.5.  PWMxCPRE 29.9.6.  PWMxPIPOS 29.9.7.  PWMxGIR 29.9.8.  PWMxGIE 29.9.9.  PWMxCON 29.9.10.  PWMxSaCFG 29.9.11.  PWMxSaP1 29.9.12.  PWMxSaP2 29.9.13.  PWMLOAD 29.9.14.  PWMEN 29.10.  Register Summary - PWM 30.  CLC - Configurable Logic Cell 30.1.  CLC Setup 30.1.1.  Data Selection 30.1.2.  Data Gating 30.1.3.  Logic Function 30.1.4.  Output Polarity 30.2.  CLC Interrupts 30.3.  Effects of a Reset 30.4.  Output Mirror Copies 30.5.  Operation During Sleep 30.6.  CLC Setup Steps 30.7.  Register Overlay 30.8.  Register Definitions: Configurable Logic Cell 30.8.1.  CLCSELECT 30.8.2.  CLCnCON 30.8.3.  CLCnPOL 30.8.4.  CLCnSEL0 30.8.5.  CLCnSEL1 30.8.6.  CLCnSEL2 30.8.7.  CLCnSEL3 30.8.8.  CLCnGLS0 30.8.9.  CLCnGLS1 30.8.10.  CLCnGLS2 30.8.11.  CLCnGLS3 30.8.12.  CLCDATA 30.9.  Register Summary - CLC Control 31.  MSSP - Host Synchronous Serial Port Module 31.1.  SPI Mode Overview 31.1.1.  SPI Mode Registers 31.1.2.  SPI Mode Operation 31.1.2.1.  SPI Host Mode 31.1.2.2.  SPI Client Mode 31.1.2.3.  Daisy-Chain Configuration 31.1.2.4.  Client Select Synchronization 31.1.2.5.  SPI Operation in Sleep Mode 31.2.  I2C Mode Overview 31.2.1.  I2C Mode Registers 31.2.2.  I2C Mode Operation 31.2.2.1.  Definition of I2C Terminology 31.2.2.2.  Byte Format 31.2.2.3.  SDA and SCL Pins 31.2.2.4.  SDA Hold Time 31.2.2.5.  Clock Stretching 31.2.2.6.  Arbitration 31.2.2.7.  Start Condition 31.2.2.8.  Stop Condition 31.2.2.9.  Start/Stop Condition Interrupt Masking 31.2.2.10.  Restart Condition 31.2.2.11.  Acknowledge Sequence 31.2.3.  I2C Client Mode Operation 31.2.3.1.  Client Mode Addresses 31.2.3.1.1.  I2C Client 7-Bit Addressing Mode 31.2.3.1.2.  I2C Client 10-Bit Addressing Mode 31.2.3.2.  Clock Stretching 31.2.3.2.1.  Normal Clock Stretching 31.2.3.2.2.  10-Bit Addressing Mode 31.2.3.2.3.  Byte NACKing 31.2.3.3.  Clock Synchronization and the CKP Bit 31.2.3.4.  General Call Address Support 31.2.3.5.  SSP Mask Register 31.2.3.6.  Client Reception 31.2.3.6.1.  7-Bit Addressing Reception 31.2.3.6.2.  7-Bit Reception with AHEN and DHEN 31.2.3.6.3.  Client Mode 10-Bit Address Reception 31.2.3.6.4.  10-Bit Addressing with Address or Data Hold 31.2.3.7.  Client Transmission 31.2.3.7.1.  Client Mode Bus Collision 31.2.3.7.2.  7-Bit Transmission 31.2.3.7.3.  7-Bit Transmission with Address Hold Enabled 31.2.4.  I2C Host Mode 31.2.4.1.  I2C Host Mode Operation 31.2.4.1.1.  Clock Arbitration 31.2.4.1.2.  WCOL Status Flag 31.2.4.1.3.  I2C Host Mode Start Condition Timing 31.2.4.1.4.  I2C Host Mode Repeated Start Condition Timing 31.2.4.1.5.  Acknowledge Sequence Timing 31.2.4.1.5.1.  Acknowledge Write Collision 31.2.4.1.6.  Stop Condition Timing 31.2.4.1.6.1.  Write Collision on Stop 31.2.4.1.7.  Sleep Operation 31.2.4.1.8.  Effects of a Reset 31.2.4.2.  I2C Host Mode Transmission 31.2.4.2.1.  BF Status Flag 31.2.4.2.2.  WCOL Status Flag 31.2.4.2.3.  ACKSTAT Status Flag 31.2.4.2.4.  Typical Transmit Sequence 31.2.4.3.  I2C Host Mode Reception 31.2.4.3.1.  BF Status Flag 31.2.4.3.2.  SSPOV Status Flag 31.2.4.3.3.  WCOL Status Flag 31.2.4.3.4.  Typical Receive Sequence 31.2.5.  Multi-Host Mode 31.2.5.1.  Multi-Host Communication, Bus Collision and Bus Arbitration 31.2.5.1.1.  Bus Collision During a Start Condition 31.2.5.1.2.  Bus Collision During a Repeated Start Condition 31.2.5.1.3.  Bus Collision During a Stop Condition 31.3.  Baud Rate Generator 31.4.  Register Definitions: MSSP Control 31.4.1.  SSPxBUF 31.4.2.  SSPxADD 31.4.3.  SSPxMSK 31.4.4.  SSPxSTAT 31.4.5.  SSPxCON1 31.4.6.  SSPxCON2 31.4.7.  SSPxCON3 31.5.  Register Summary - MSSP Control 32.  EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter 32.1.  EUSART Asynchronous Mode 32.1.1.  EUSART Asynchronous Transmitter 32.1.1.1.  Enabling the Transmitter 32.1.1.2.  Transmitting Data 32.1.1.3.  Transmit Data Polarity 32.1.1.4.  Transmit Interrupt Flag 32.1.1.5.  TSR Status 32.1.1.6.  Transmitting 9-Bit Characters 32.1.1.7.  Asynchronous Transmission Setup 32.1.2.  EUSART Asynchronous Receiver 32.1.2.1.  Enabling the Receiver 32.1.2.2.  Receiving Data 32.1.2.3.  Receive Interrupts 32.1.2.4.  Receive Framing Error 32.1.2.5.  Receive Overrun Error 32.1.2.6.  Receiving 9-Bit Characters 32.1.2.7.  Address Detection 32.1.2.8.  Asynchronous Reception Setup 32.1.2.9.  9-Bit Address Detection Mode Setup 32.2.  Clock Accuracy with Asynchronous Operation 32.3.  EUSART Baud Rate Generator (BRG) 32.3.1.  Auto-Baud Detect 32.3.2.  Auto-Baud Overflow 32.3.3.  Auto-Wake-Up on Break 32.3.3.1.  Special Considerations 32.3.4.  Break Character Sequence 32.3.4.1.  Break and Sync Transmit Sequence 32.3.5.  Receiving a Break Character 32.4.  EUSART Synchronous Mode 32.4.1.  Synchronous Host Mode 32.4.1.1.  Host Clock 32.4.1.2.  Clock Polarity 32.4.1.3.  Synchronous Host Transmission 32.4.1.4.  Synchronous Host Transmission Setup 32.4.1.5.  Synchronous Host Reception 32.4.1.6.  Client Clock 32.4.1.7.  Receive Overrun Error 32.4.1.8.  Receiving 9-Bit Characters 32.4.1.9.  Synchronous Host Reception Setup 32.4.2.  Synchronous Client Mode 32.4.2.1.  EUSART Synchronous Client Transmit 32.4.2.2.  Synchronous Client Transmission Setup 32.4.2.3.  EUSART Synchronous Client Reception 32.4.2.4.  Synchronous Client Reception Setup 32.5.  EUSART Operation During Sleep 32.5.1.  Synchronous Receive During Sleep 32.5.2.  Synchronous Transmit During Sleep 32.6.  Register Definitions: EUSART Control 32.6.1.  TXxSTA 32.6.2.  RCxSTA 32.6.3.  BAUDxCON 32.6.4.  RCxREG 32.6.5.  TXxREG 32.6.6.  SPxBRG 32.7.  Register Summary - EUSART 33.  ADC - Analog-to-Digital Converter with Computation Module 33.1.  ADC Configuration 33.1.1.  ADC Input Configuration 33.1.2.  Port Configuration 33.1.3.  Channel Selection 33.1.3.1.  Channel Grouping 33.1.4.  ADC Voltage Reference 33.1.5.  Conversion Clock 33.1.6.  Interrupts 33.1.7.  Result Formatting 33.1.7.1.  Sign/Magnitude and Two’s Complement Result 33.2.  ADC Operation 33.2.1.  Starting a Conversion 33.2.2.  Completion of a Conversion 33.2.3.  ADC Operation During Sleep 33.2.4.  External Trigger During Sleep 33.2.5.  Auto-Conversion Trigger 33.2.6.  ADC Conversion Procedure (Basic Mode) 33.3.  ADC Acquisition Requirements 33.4.  Computation Operation 33.4.1.  Digital Filter/Average 33.4.2.  Basic Mode 33.4.3.  Accumulate Mode 33.4.4.  Average Mode 33.4.5.  Burst Average Mode 33.4.6.  Low-Pass Filter Mode 33.4.7.  Threshold Comparison 33.4.8.  Repetition and Sampling Options 33.4.8.1.  Continuous Sampling Mode 33.4.8.2.  Double Sample Conversion 33.4.9.  Capacitive Voltage Divider (CVD) Features 33.4.9.1.  CVD Operation 33.4.9.2.  Precharge Control 33.4.9.3.  Acquisition Control for CVD (ADPRE > 0) 33.4.9.4.  Guard Ring Outputs 33.4.9.5.  Additional Sample-and-Hold Capacitance 33.5.  Register Definitions: ADC Control 33.5.1.  ADCON0 33.5.2.  ADCON1 33.5.3.  ADCON2 33.5.4.  ADCON3 33.5.5.  ADSTAT 33.5.6.  ADCLK 33.5.7.  ADREF 33.5.8.  ADPCH 33.5.9.  ADNCH 33.5.10.  ADPRE 33.5.11.  ADACQ 33.5.12.  ADCAP 33.5.13.  ADRPT 33.5.14.  ADCNT 33.5.15.  ADFLTR 33.5.16.  ADRES 33.5.17.  ADPREV 33.5.18.  ADACC 33.5.19.  ADSTPT 33.5.20.  ADERR 33.5.21.  ADLTH 33.5.22.  ADUTH 33.5.23.  ADACT 33.5.24.  ADCGxA 33.5.25.  ADCGxB 33.5.26.  ADCGxC 33.6.  Register Summary - ADC 34.  OPA - Operational Amplifier 34.1.  OPA Module Control 34.1.1.  Unity Gain Mode 34.1.2.  Programmable Source Selection 34.1.3.  Programmable Gain Options 34.2.  Hardware Override Control 34.3.  Input Offset Voltage 34.3.1.  Offset Calibration 34.4.  OPA Operation with ADC 34.5.  Register Definitions: Operational Amplifier 34.5.1.  OPAxCON0 34.5.2.  OPAxCON1 34.5.3.  OPAxCON2 34.5.4.  OPAxCON3 34.5.5.  OPAxHWC 34.5.6.  OPAxOFFSET 34.5.7.  OPAxORS 34.6.  Register Summary - Operational Amplifier 35.  DAC - Digital-to-Analog Converter Module 35.1.  Output Voltage Selection 35.2.  Ratiometric Output Level 35.3.  Buffered DAC Output Range Selection 35.4.  Operation During Sleep 35.5.  Effects of a Reset 35.6.  Register Definitions: DAC Control 35.6.1.  DACxCON 35.6.2.  DACxDATL 35.7.  Register Summary - DAC 36.  CMP - Comparator Module 36.1.  Comparator Overview 36.2.  Comparator Control 36.2.1.  Comparator Enable 36.2.2.  Comparator Output 36.2.3.  Comparator Output Polarity 36.3.  Comparator Output Synchronization 36.4.  Comparator Hysteresis 36.5.  Comparator Interrupt 36.6.  Comparator Positive Input Selection 36.7.  Comparator Negative Input Selection 36.8.  Comparator Response Time 36.9.  Analog Input Connection Considerations 36.10.  Operation in Sleep Mode 36.11.  ADC Auto-Trigger Source 36.12.  Register Definitions: Comparator Control 36.12.1.  CMxCON0 36.12.2.  CMxCON1 36.12.3.  CMxNCH 36.12.4.  CMxPCH 36.12.5.  CMOUT 36.13.  Register Summary - Comparator 37.  FVR - Fixed Voltage Reference 37.1.  Independent Gain Amplifiers 37.2.  FVR Stabilization Period 37.3.  Register Definitions: FVR 37.3.1.  FVRCON 37.4.  Register Summary - FVR 38.  Temperature Indicator Module 38.1.  Module Operation 38.1.1.  Temperature Indicator Range 38.1.2.  Minimum Operating VDD 38.2.  Temperature Calculation 38.3.  ADC Acquisition Time 38.4.  Register Definitions: Temperature Indicator 38.4.1.  FVRCON 38.5.  Register Summary - Temperature Indicator 39.  ZCD - Zero-Cross Detection Module 39.1.  External Resistor Selection 39.2.  ZCD Logic Output 39.3.  ZCD Logic Polarity 39.4.  ZCD Interrupts 39.5.  Correction for ZCPINV Offset 39.5.1.  Correction by AC Coupling 39.5.2.  Correction by Offset Current 39.6.  Handling VPEAK Variations 39.7.  Operation During Sleep 39.8.  Effects of a Reset 39.9.  Disabling the ZCD Module 39.10.  Register Definitions: ZCD Control 39.10.1.  ZCDCON 39.11.  Register Summary - ZCD 40.  Charge Pump 40.1.  Manually Enabled 40.2.  Automatically Enabled 40.3.  Disabled 40.4.  Charge Pump Oscillator 40.5.  Charge Pump Threshold 40.6.  Charge Pump Ready 40.7.  Register Definitions: Charge Pump 40.7.1.  CPCON 40.8.  Register Summary - Charge Pump 41.  Instruction Set Summary 41.1.  Read-Modify-Write Operations 41.2.  Standard Instruction Set 41.2.1.  Standard Instruction Set
 42.  ICSP™ - In-Circuit Serial Programming™ 42.1.  High-Voltage Programming Entry Mode 42.2.  Low-Voltage Programming Entry Mode 42.3.  Common Programming Interfaces 43.  Register Summary 44.  Electrical Specifications 44.1.  Absolute Maximum Ratings(†) 44.2.  Standard Operating Conditions 44.3.  DC Characteristics 44.3.1.  Supply Voltage 44.3.2.  Supply Current (IDD)(1,2) 44.3.3.  Power-Down Current (IPD)(1,2,3) 44.3.4.  I/O Ports 44.3.5.  Memory Programming Specifications 44.3.6.  Thermal Characteristics 44.4.  AC Characteristics 44.4.1.  External Clock/Oscillator Timing Requirements 44.4.2.  Internal Oscillator Parameters(1) 44.4.3.  I/O and CLKOUT Timing Specifications 44.4.4.  Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications 44.4.5.  Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 44.4.6.  Analog-to-Digital Converter (ADC) Conversion Timing Specifications 44.4.7.  Operational Amplifier Specifications 44.4.8.  8-Bit DAC Specifications 44.4.9.  Comparator Specifications 44.4.10.  Zero-Cross Detect (ZCD) Specifications 44.4.11.  Fixed Voltage Reference (FVR) Specifications 44.4.12.  Temperature Indicator Requirements 44.4.13.  Timer0 and Timer1 External Clock Requirements 44.4.14.  Capture/Compare/PWM Requirements (CCP) 44.4.15.  EUSART Synchronous Transmission Requirements 44.4.16.  EUSART Synchronous Receive Requirements 44.4.17.  SPI Mode Requirements 44.4.18.  I2C Bus Start/Stop Bits Requirements 44.4.19.  I2C Bus Data Requirements 44.4.20.  Configurable Logic Cell (CLC) Characteristics 45.  DC and AC Characteristics Graphs and Tables 46.  Packaging Information 46.1.  Package Details 47.  Appendix A: Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service