Datasheet TPV803, TPV809, TPV810 (3PEAK) - 8
| Fabricante | 3PEAK |
| Descripción | Low Voltage Supervisory Circuit |
| Páginas / Página | 15 / 8 — TPV803/809/810. Low Voltage Supervisory Circuit. Detailed Description. … |
| Formato / tamaño de archivo | PDF / 708 Kb |
| Idioma del documento | Inglés |
TPV803/809/810. Low Voltage Supervisory Circuit. Detailed Description. Overview. Functional Block Diagram
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Versión de texto del documento
TPV803/809/810 Low Voltage Supervisory Circuit Detailed Description Overview
The TPV803/809/810 provides supply voltage supervision function. A reset signal is asserted when the supply voltage is below a preset threshold. In addition, the TPV803/809/810 allows supply voltage stabilization with a fixed timeout before the reset de-asserts after the supply voltage rises above the threshold.
Functional Block Diagram Figure 7 Functional Block Diagram Feature Description
The TPV803/809 feature an active-low open-drain or push-pull output. The TPV8810 features an active-high push-pull output. For active-low output, the reset signal is guaranteed to be logic low for VCC down to 1 V. For active-high output, the reset signal is guaranteed to be logic low for VCC down to 1 V. The reset output is asserted when VCC is below the reset threshold (VTH), Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold. Figure 8 shows the reset outputs.
Figure 8 Reset Timing Diagram www.3peakic.com.cn 8 / 15 Rev.A.5
The TPV803/809/810 provides supply voltage supervision function. A reset signal is asserted when the supply voltage is below a preset threshold. In addition, the TPV803/809/810 allows supply voltage stabilization with a fixed timeout before the reset de-asserts after the supply voltage rises above the threshold.
Functional Block Diagram Figure 7 Functional Block Diagram Feature Description
The TPV803/809 feature an active-low open-drain or push-pull output. The TPV8810 features an active-high push-pull output. For active-low output, the reset signal is guaranteed to be logic low for VCC down to 1 V. For active-high output, the reset signal is guaranteed to be logic low for VCC down to 1 V. The reset output is asserted when VCC is below the reset threshold (VTH), Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold. Figure 8 shows the reset outputs.
Figure 8 Reset Timing Diagram www.3peakic.com.cn 8 / 15 Rev.A.5