Datasheet L6562 (STMicroelectronics) - 5
| Fabricante | STMicroelectronics |
| Descripción | Transition-Mode PFC Controller |
| Páginas / Página | 16 / 5 — L6562. Typical Electrical Characteristics. Figure 4. Supply current vs. … |
| Idioma del documento | Inglés |
L6562. Typical Electrical Characteristics. Figure 4. Supply current vs. Supply voltage. Figure 6. IC consumption vs. T
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L6562 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 6. IC consumption vs. T
j ICC Icc 10 (mA) [mA] 5 Operating 10 Quiescent 2 5 1 Disabled or 1 during OVP 0.5 0.5 Vcc = 12 V Co = 1 nF 0.1 0.2 f = 70 kHz 0.05 Co = 1nF 0.1 0.01 f = 70 kHz Before start-up T 0.05 0.005 j = 25°C 0 0.02 0 5 10 15 20 25 -50 0 50 100 150 Vcc(V) Tj (°C)
Figure 5. Start-up & UVLO vs. T Figure 7. Vcc Zener voltage vs. T
j j
VccZ 12.5 28 (V) VCC-ON (V) 12 27 11.5 26 11 25 10.5 24 10 VCC-OFF 9.5 23 (V) 9 22 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
5/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History
j ICC Icc 10 (mA) [mA] 5 Operating 10 Quiescent 2 5 1 Disabled or 1 during OVP 0.5 0.5 Vcc = 12 V Co = 1 nF 0.1 0.2 f = 70 kHz 0.05 Co = 1nF 0.1 0.01 f = 70 kHz Before start-up T 0.05 0.005 j = 25°C 0 0.02 0 5 10 15 20 25 -50 0 50 100 150 Vcc(V) Tj (°C)
Figure 5. Start-up & UVLO vs. T Figure 7. Vcc Zener voltage vs. T
j j
VccZ 12.5 28 (V) VCC-ON (V) 12 27 11.5 26 11 25 10.5 24 10 VCC-OFF 9.5 23 (V) 9 22 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
5/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History