Datasheet SKY53510 (Skyworks) - 8
| Fabricante | Skyworks |
| Descripción | 10-Output Ulta Low Additive Jitter Clock Buffer |
| Páginas / Página | 51 / 8 — DATA SHEET. SKY53510/SKY53580/SKY53540. 1.3. SKY53540 5x5 mm 32-QFN Pin … |
| Formato / tamaño de archivo | PDF / 5.1 Mb |
| Idioma del documento | Inglés |
DATA SHEET. SKY53510/SKY53580/SKY53540. 1.3. SKY53540 5x5 mm 32-QFN Pin Descriptions. Figure 4. SKY53540 5x5 mm 32-QFN Pinout
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DATA SHEET SKY53510/SKY53580/SKY53540 1.3. SKY53540 5x5 mm 32-QFN Pin Descriptions
T1 C U EF UT R O b O _ D O D 1 K 1 K SF OE VD REF VD CL CL NC
32 31 30 29 28 27 26 25
GND
1 24
GND VDDOA
2 23
VDDOB Q0
3 22
Q2 Q0b
4 21
Q2b VDDOA
5 20
VDDOB Q1
6 19
Q3 Q1b
7 18
Q3b GND
8 17
GND
9 10 11 12 13 14 15 16
0 b T0 D XA XB K 0 U VD K SEL1 O SEL0 _ CL CL _ K SF K CL CL
Figure 4. SKY53540 5x5 mm 32-QFN Pinout Table 3. SKY53540 5x5 mm 32-QFN Pin Descriptions Pin Name Type1 Description
1 GND GND Ground. 2 VDDOA P Output voltage supply-Bank A (Outputs: Q0 to Q1). Bypass with 0.1 µF capacitor and place as close to the VDDOA pin as possible. 3 Q0 O Output clock 0. 4 Q0b O Output clock 0 (complement). Output voltage supply-Bank A (Outputs: Q0 to Q1). 5 VDDOA P Bypass with 1.0 µF capacitor and place as close to the VDDOA pin as possible. 6 Q1 O Output clock 1. 7 Q1b O Output clock 1 (complement). 8 GND GND Ground. Output signal format control pin for Bank A and Bank B. 9 SFOUT0 I SFOUT0 contains an internal pull-down resistor. Core voltage supply. 10 VDD P Bypass with 0.1 µF capacitor placed as close to the VDD pin as possible. 11 XA I Crystal input. Can also be driven by a XO, TCXO, or other external single-ended clock. 12 XB O Crystal output. When a crystal is not used and XA is used as an input, this pin should be left floating. 13 CLK_SEL0 I Mux input select pin. CLK_SEL0 contains an internal pull-down resistor. 14 CLK0 I Input clock 0. Skyworks Solutions, Inc. • Phone [949] 231-3000 • sales@skyworksinc.com • www.skyworksinc.com 207106A • Skyworks Proprietary Information • Products and Product Information are Subject to Change without Notice 8 August 1, 2025 Document Outline Key Features 1. Pin Descriptions 1.1. SKY53510 7x7 mm 48-QFN Pin Descriptions 1.2. SKY53580 6x6 mm 40-QFN Pin Descriptions 1.3. SKY53540 5x5 mm 32-QFN Pin Descriptions 2. Detailed Description 2.1. Overview 2.2. Block Diagrams 2.3. Modes of Operation 2.3.1. Input Clock Stage 2.3.2. Clock Outputs 3. Applications Information 3.1. Driving Clock Inputs (CLK0/CLK1) 3.2. Crystal Interface (XA/XB) 3.3. Clock Output Termination 3.3.1. DC-Coupled Differential Output Driver Terminations 3.3.2. AC-Coupled Differential Output Driver Terminations 4. Power Supply (VDD and VDDOx) 4.1. Power Supply Sequencing 5. Electrical Specifications 6. Typical Performance Characteristics 7. Package and Handling Information 7.1. 48-QFN Package Diagram 7.2. 40-QFN Package Diagram 7.3. 32-QFN Package Diagram 8. Land Patterns 8.1. 48-QFN Land Pattern 8.2. 40-QFN Land Pattern 8.3. 32-QFN Land Pattern 9. Top Markings 9.1. SKY53510/80/40 Top Markings 10. Ordering Guide 11. Revision History
T1 C U EF UT R O b O _ D O D 1 K 1 K SF OE VD REF VD CL CL NC
32 31 30 29 28 27 26 25
GND
1 24
GND VDDOA
2 23
VDDOB Q0
3 22
Q2 Q0b
4 21
Q2b VDDOA
5 20
VDDOB Q1
6 19
Q3 Q1b
7 18
Q3b GND
8 17
GND
9 10 11 12 13 14 15 16
0 b T0 D XA XB K 0 U VD K SEL1 O SEL0 _ CL CL _ K SF K CL CL
Figure 4. SKY53540 5x5 mm 32-QFN Pinout Table 3. SKY53540 5x5 mm 32-QFN Pin Descriptions Pin Name Type1 Description
1 GND GND Ground. 2 VDDOA P Output voltage supply-Bank A (Outputs: Q0 to Q1). Bypass with 0.1 µF capacitor and place as close to the VDDOA pin as possible. 3 Q0 O Output clock 0. 4 Q0b O Output clock 0 (complement). Output voltage supply-Bank A (Outputs: Q0 to Q1). 5 VDDOA P Bypass with 1.0 µF capacitor and place as close to the VDDOA pin as possible. 6 Q1 O Output clock 1. 7 Q1b O Output clock 1 (complement). 8 GND GND Ground. Output signal format control pin for Bank A and Bank B. 9 SFOUT0 I SFOUT0 contains an internal pull-down resistor. Core voltage supply. 10 VDD P Bypass with 0.1 µF capacitor placed as close to the VDD pin as possible. 11 XA I Crystal input. Can also be driven by a XO, TCXO, or other external single-ended clock. 12 XB O Crystal output. When a crystal is not used and XA is used as an input, this pin should be left floating. 13 CLK_SEL0 I Mux input select pin. CLK_SEL0 contains an internal pull-down resistor. 14 CLK0 I Input clock 0. Skyworks Solutions, Inc. • Phone [949] 231-3000 • sales@skyworksinc.com • www.skyworksinc.com 207106A • Skyworks Proprietary Information • Products and Product Information are Subject to Change without Notice 8 August 1, 2025 Document Outline Key Features 1. Pin Descriptions 1.1. SKY53510 7x7 mm 48-QFN Pin Descriptions 1.2. SKY53580 6x6 mm 40-QFN Pin Descriptions 1.3. SKY53540 5x5 mm 32-QFN Pin Descriptions 2. Detailed Description 2.1. Overview 2.2. Block Diagrams 2.3. Modes of Operation 2.3.1. Input Clock Stage 2.3.2. Clock Outputs 3. Applications Information 3.1. Driving Clock Inputs (CLK0/CLK1) 3.2. Crystal Interface (XA/XB) 3.3. Clock Output Termination 3.3.1. DC-Coupled Differential Output Driver Terminations 3.3.2. AC-Coupled Differential Output Driver Terminations 4. Power Supply (VDD and VDDOx) 4.1. Power Supply Sequencing 5. Electrical Specifications 6. Typical Performance Characteristics 7. Package and Handling Information 7.1. 48-QFN Package Diagram 7.2. 40-QFN Package Diagram 7.3. 32-QFN Package Diagram 8. Land Patterns 8.1. 48-QFN Land Pattern 8.2. 40-QFN Land Pattern 8.3. 32-QFN Land Pattern 9. Top Markings 9.1. SKY53510/80/40 Top Markings 10. Ordering Guide 11. Revision History