Datasheet Si5351 (Silicon Labs) - 10

S i 5 3 5 1 A / B / C - B 2. Detailed Block Diagrams
VDD VDDO
Si5351A 3-Output
PLL MultiSynth A R0 CLK0 0 XA OSC PLL XB MultiSynth B R1 CLK1 1 SDA I2C MultiSynth R2 CLK2 Interface SCL 2 GND
10-MSOP
VDD
Si5351A 8-Output
VDDOA MultiSynth PLL R0 0 CLK0 A XA MultiSynth CLK1 R1 OSC 1 PLL VDDOB XB MultiSynth B R2 2 CLK2 MultiSynth CLK3 R3 3 A0 VDDOC MultiSynth I2C R4 4 CLK4 SDA Interface MultiSynth CLK5 SCL R5 5 VDDOD MultiSynth R6 OEB 6 CLK6 Control Logic MultiSynth CLK7 SSEN R7 7 GND
20-QFN Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices 10 Rev. 1.0
Document Outline 1. Electrical Specifications 2. Detailed Block Diagrams 3. Functional Description 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) 3.1.2. External Clock Input (CLKIN) 3.1.3. Voltage Control Input (VC) 3.2. Synthesis Stages 3.3. Output Stage 3.4. Spread Spectrum 3.5. Control Pins (OEB, SSEN) 3.5.1. Output Enable (OEB) 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only 4. I2C Interface 5. Configuring the Si5351 5.1. Writing a Custom Configuration to RAM 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs 5.5. Replacing Crystals, Crystal Oscillators, and PLLs 5.6. Applying a Reference Clock at XTAL Input 5.7. HCSL Compatible Outputs 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.5. Unused Pins 6.6. Trace Characteristics 7. Register Map Summary 8. Register Descriptions 9. Si5351 Pin Descriptions 9.1. Si5351A 20-pin QFN 9.2. Si5351B 20-Pin QFN 9.3. Si5351C 20-Pin QFN 9.4. Si5351A 10-Pin MSOP 10. Ordering Information 11. Package Outlines 11.1. 20-pin QFN 12. Land Pattern: 20-Pin QFN 12.1. 10-Pin MSOP Package Outline 13. Land Pattern: 10-Pin MSOP 14. Top Marking 14.1. 20-Pin QFN Top Marking 14.2. Top Marking Explanation 14.3. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Document Change List