Datasheet Si5351 (Skyworks)

link to page 34
Si5351A/B/C-B I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR + VCXO Features
https://www.skyworksinc.com/Products/Timi Glitchless frequency changes ng/CMOS-Clock-Generators
10-MSOP
Separate voltage supply pins Generates up to eight non-integer- provide level translation: related frequencies from 2.5 kHz to Core VDD: 2.5 or 3.3 V 200 MHz Output VDDO: 1.8, 2.5, or 3.3 V I2C user definable configuration Excellent PSRR eliminates external Exact frequency synthesis at each power supply filtering output (0 ppm error) Very low power consumption Highly linear VCXO
16-QFN
Adjustable output delay Optional clock input (CLKIN) Available in three packages types: Low output period jitter: < 70 ps pp, 10-MSOP: 3 outputs typ 16-QFN (3x3 mm): 4 outputs Configurable spread spectrum selectable at each output 20-QFN (4x4 mm): 8 outputs PCIE Gen 1 compatible Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz Supports HCSL compatible swing
20-QFN
Supports static phase offset Programmable rise/fall time control
Applications
Audio/video equipment, gaming Residential gateways Printers, scanners, projectors Networking/communication Handheld Instrumentation Servers, storage
Ordering Information:
Laser range finder XO replacement See page 34
Description
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide variety of applications. The Si5351A generates up to 8 free-running clocks using an internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an internal VCXO and provides the flexibility to replace both free-running clocks and synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while providing reliable operation over a wide tuning range. The Si5351C offers the same flexibility but synchronizes to an external reference clock (CLKIN). Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021 Document Outline 1. Ordering Guide 2. Technical Support Resources 3. Electrical Specifications 4. Functional Description 4.1. Input Stage 4.1.1. Crystal Inputs (XA, XB) 4.1.2. External Clock Input (CLKIN) 4.1.3. Voltage Control Input (VC) 4.2. Synthesis Stages 4.3. Output Stage 4.4. Spread Spectrum 4.5. Control Pins (OEB, SSEN) 4.5.1. Output Enable (OEB) 4.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B Only 4.6. Status Pins (INTR) 5. I2C Interface 6. Configuring the Si5351 6.1. Writing a Custom Configuration to RAM 6.2. Si5351 Application Examples 6.3. Replacing Crystals and Crystal Oscillators 6.4. Replacing Crystals, Crystal Oscillators, and VCXOs 6.5. Replacing Crystals, Crystal Oscillators, and PLLs 6.6. Applying a Reference Clock at XTAL Input 6.7. HCSL Compatible Outputs 7. Design Considerations 7.1. Power Supply Decoupling/Filtering 7.2. Power Supply Sequencing 7.3. External Crystal 7.4. External Crystal Load Capacitors 7.5. Unused Pins 7.6. Trace Characteristics 8. Register Map Summary 9. Register Descriptions 10. Si5351 Pin Descriptions 10.1. Si5351A 20-pin QFN 10.2. Si5351B 20-Pin QFN 10.3. Si5351C 20-Pin QFN 10.4. Si5351A 16-Pin QFN 10.5. Si5351B 16-Pin QFN 10.6. Si5351C 16-Pin QFN 10.7. Si5351A 10-Pin MSOP 11. Ordering Information 12. Packaging 12.1. 20-pin QFN Package Outline 12.2. Land Pattern: 20-Pin QFN 12.3. 16-Pin QFN Package Outline 12.4. Land Pattern: 16-Pin QFN 12.5. 10-Pin MSOP Package Outline 12.6. Land Pattern: 10-Pin MSOP 13. Top Marking 13.1. 20-Pin QFN Top Marking 13.2. Top Marking Explanation 13.3. 16-Pin QFN Top Marking 13.4. Top Marking Explanation 13.5. 10-Pin MSOP Top Marking 13.6. Top Marking Explanation Revision History