Datasheet RTL2832U (Realtek) - 3

RTL2832U
Datasheet Table of Contents
1. GENERAL DESCRIPTION .1 2. FEATURES .2 3. SYSTEM APPLICATIONS.2 4. BLOCK DIAGRAM .3 5. PIN ASSIGNMENTS .4
5.1. k
e
t GREEN PACKAGE AND VERSION IDENTIFICATION .4 6. PIN DESCRIPTIONS.5 7. FUNCTIONAL DESCRIPTION.7
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11. 8. ANALOG-TO-DIGITAL CONVERSION (ADC).7
AUTOMATIC GAIN CONTROL (AGC).7
DIGITAL DOWN CONVERSION .7
RESAMPLER .8
GUARD INTERVAL REMOVAL .8
FAST FOURIER TRANSFORM (FFT).8
SYNCHRONIZATION .8
CHANNEL ESTIMATION .9
TRANSMISSION PARAMETER SIGNAL DECODER .9
EQUALIZATION .9
DE-INTERLEAVER, FEC DECODER, AND DESCRAMBLER .9 l
a e
R L
IA T
N TUNER INTERFACE.10 E
ID 8.1.
AUTOMATIC GAIN CONTROL (AGC).11
8.1.1. Register Name: loop_gain .12
8.1.2. Register Name: if_agc_min/if_agc_max/rf_agc_min/rf_agc_max .13
8.1.3. Register Name: Vtop.13
8.1.4. Register Name: Krf.14
8.1.5. Register Name: if_agc_val/rf_agc_val .14
8.2.
ADC INPUT (TUNER OUTPUT) .14
8.3.
TWO-WIRE INTERFACE BETWEEN THE TUNER AND THE RTL2832U .15
8.4.
RTL2832U INTERNAL SWITCHING REGULATOR .16
9. F
N O
C REGISTER DESCRIPTIONS (GENERAL).17
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
9.8.
9.9.
9.10.
9.11. 10. L
4
V ANALOG TO DIGITAL CONVERTER (ADC) .17
DC CANCELLATION AND IQ COMPENSATION .18
DIGITAL DOWN CONVERSION (DDC) .19
RESAMPLER .20
CO-CHANNEL INTERFERENCE REJECTION .21
IMPULSE NOISE CANCELLATION .21
DIGITAL AUTOMATIC GAIN CONTROL (DAGC) .22
FFT MODE DETECTION .22
TIMING RECOVERY/CARRIER RECOVERY .23
CRYSTAL.24
PID FILTER .24 r
fo REGISTER DESCRIPTIONS (8051 SYSTEM) .27 10.1.
DEMODULATOR CONTROL REGISTER (DEMOD_CTL, 0000H) .29
10.2.
GPIO RELATED REGISTERS (0001H~0008H) .29
10.2.1.
GPIO Output Value Register (GPO, 0001h) .30
DVB-T COFDM Demodulator + USB 2.0 iii Track ID: JATR-2265-11 Rev. 1.4