Datasheet MPF4392 (ON Semiconductor) - 4

MPF4392, MPF4393 NOTE 1
The switching characteristics shown above were measured using a VDD test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (−VGG). The RD Drain−Source Voltage (VDS) is slightly lower than Drain Supply SET V Voltage (V DS(off) = 10 V DD) due to the voltage divider. Thus Reverse Transfer Capacitance (C INPUT rss) or Gate−Drain Capacitance (Cgd) is charged to RK R V T GG + VDS. R During the turn−on interval, Gate−Source Capacitance (C GEN OUTPUT gs) 50 W R discharges through the series combination of R GG Gen and RK. Cgd 50 50 must discharge to VDS(on) through RG and RK in series with the W V W V GG parallel combination of effective load impedance (R GEN D) and Drain−Source Resistance (rds). During the turn−off, this charge flow is reversed. INPUT PULSE RGG & RK Predicting turn−on time is somewhat difficult as the channel tr  0.25 ns resistance rds is a function of the gate−source voltage. While Cgs t RD = RD(RT + 50) f  0.5 ns discharges, VGS approaches zero and rds decreases. Since Cgd PULSE WIDTH = 2.0 ms RD + RT + 50 discharges through r DUTY CYCLE  2.0% ds, turn−on time is non−linear. During turn−off, the situation is reversed with rds increasing as Cgd charges.
Figure 5. Switching Time Test Circuit
The above switching curves show two impedance conditions: 1) RK is equal to RD which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. 20 15 MPF4392 10 ANCE (mmhos) Cgs 10 7.0 ADMITT MPF4393 7.0 ANCE (pF) 5.0 Cgd ACIT 5.0 T TRANSFER channel = 25C Tchannel = 25C VDS = 15 V 3.0 C, CAP (C ARD ds IS NEGLIGIBLE) 2.0 W 3.0 1.5 , FOR fsy 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30 I V D, DRAIN CURRENT (mA) R, REVERSE VOLTAGE (VOLTS)
Figure 6. Typical Forward Transfer Admittance Figure 7. Typical Capacitance
2.0 200 IDSS 25 50 mA 75 mA 100 mA 125 mA E I E 1.8 D = 1.0 mA = 10 mA T T A A VGS = 0 160 mA 1.6 1.4 120 1.2 80 ANCE (NORMALIZED) ANCE (OHMS) 1.0 , DRAIN-SOURCE ON-ST , DRAIN-SOURCE ON-ST 0.8 RESIST RESIST 40 ds(on) r ds(on) r 0.6 Tchannel = 25C 0.4 0 -70 -40 -10 20 50 80 110 140 170 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 T V channel, CHANNEL TEMPERATURE (C) GS, GATE-SOURCE VOLTAGE (VOLTS)
Figure 8. Effect of Gate−Source Voltage Figure 9. Effect of Temperature On On Drain−Source Resistance Drain−Source On−State Resistance http://onsemi.com 4