Datasheet PAC1811 (Microchip) - 9
| Fabricante | Microchip |
| Descripción | 42V Power Monitor with I2C and Alert, 16--bit |
| Páginas / Página | 92 / 9 — PAC1811. Note:. = 3.3V. of Full Scale). Error (%. BUSV. ▬ T = -40°C. ▬ T … |
| Formato / tamaño de archivo | PDF / 2.3 Mb |
| Idioma del documento | Inglés |
PAC1811. Note:. = 3.3V. of Full Scale). Error (%. BUSV. ▬ T = -40°C. ▬ T = 0°C. ▬ T = +25°C. BUS. ▬ T = +85°C. ▬ T = +125°C. (V). FIGURE 2-13:
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Versión de texto del documento
PAC1811 Note:
Unless otherwise indicated, TA = -40°C to +125°C, VDD = 2.7V to 5.5V, VBUS = 0V to 42V, VSENSE = VSENSE+ – VSENSE– = 0V. 0.05 2
V = 3.3V V = 3.3V DD DD
0.025 0 0 -2
)
-0.025 -4 -0.05 -6
of Full Scale) Error (%
-0.075 -8
BUSV
-0.1
▬ T = -40°C A Error (%
-10
▬ T = 0°C ▬ T = -40°C A A
-0.125
▬ T = +25°C ▬ T = 0°C A A BUS ▬ T = +85°C ▬ T = +25°C A
-12
A V ▬ T = +125°C
-0.15
▬ T = +85°C A A ▬ T = +125°C A
-14 -0.175 0.01 0.1 1 10 0 5 10 15 20 25 30 35 40 45
V (V) BUS V (V) BUS FIGURE 2-13:
VBUS Error vs. VBUS,
FIGURE 2-16:
VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. Logarithmic Scale, Zoom View. 0.02 3000
V = 3.3V ▬ T = -40°C DD x = -6.07 μV A otal)
0.015
▬ T = 0°C σ = 2.29 μV A T ▬ T = +25°C
2500
LSBs = 1.5 μV A ▬ T = +85°C V = 10.5V BUS
0.01
A ▬ T = +125°C A
2000 0.005
of Full Scale)
1500 0
Samples (10,000
-0.005 1000
SENSEV Error (%
-0.01 500
BUSV
-0.015 0
Number of
3 -0.02 -9.16 -7.63 -6.10 -4.58 -3.05 -1.53 0.00 1.5 3.05 4.58 6.10 7.63 9.16 -5 0 5 10 15 20 25 30 35 40 45 -15.26 -13.73 -12.21 -10.68 10.68 12.21 13.73 15.26
V (V) V Offset (μV) BUS SENSE FIGURE 2-14:
VBUS Error vs. VBUS,
FIGURE 2-17:
VSENSE Offset Histogram, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. Bipolar FSR/2 Mode, n = 10,000 Total Samples, 8x Average. 0.03 3000
▬ T = -40°C x = -1.21 mV A V = 3.3V DD ▬ T = 0°C otal) σ = 1.03 mV A LSBs = 0.64 mV
0.02
▬ T = +25°C
2500
A V = 3.3V ▬ T = +85°C DD A ▬ T = +125°C A
2000 0.01
of Full Scale)
1500 0
Samples (10,000 T BUS
1000 -0.01
V Error (%
500
BUS
-0.02
V Number of
0 -0.03 -4 -1 2 5 2.6 3.2 3.8 4.4 5.6 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -6.4 -5.8 -5.2 -4.6 -3.4 -2.8 -2.2 -1.6 -0.4 0.2 0.8 1.4
V (V) V ADC Output (mV) BUS BUS FIGURE 2-15:
VBUS Error vs. VBUS,
FIGURE 2-18:
VBUS Offset Histogram, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Bipolar FSR/2 Mode, n = 10,000 Total Samples, Zoom View. 8x Average. 2025 Microchip Technology Inc. and its subsidiaries DS20007066B-page 9 Document Outline Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features Applications Description Package Types Functional Block Diagram 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings (†) FIGURE 1-1: PAC1811 ESD Protection Circuitry. 1.2 DC Electrical Specifications 1.3 AC Electrical Specifications 1.4 Temperature Specifications 2.0 Typical Performance Curves FIGURE 2-1: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. FIGURE 2-2: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. FIGURE 2-3: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. FIGURE 2-4: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode. FIGURE 2-5: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode. FIGURE 2-6: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode. FIGURE 2-7: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-8: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-9: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-10: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-11: VBUS Error vs. VBUS, VDD = 3.3V, TA = 25°C, Unipolar Mode, Logarithmic Scale. FIGURE 2-12: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-13: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale, Zoom View. FIGURE 2-14: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-15: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-16: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-17: VSENSE Offset Histogram, Bipolar FSR/2 Mode, n = 10,000 Total Samples, 8x Average. FIGURE 2-18: VBUS Offset Histogram, Bipolar FSR/2 Mode, n = 10,000 Total Samples, 8x Average. FIGURE 2-19: VBUS Offset vs. TA, VDD = 3.3V, Bipolar FSR Mode. FIGURE 2-20: VSENSE DC Offset vs. TA, VBUS = 10.5V, Bipolar FSR Mode. FIGURE 2-21: IDD at ƒS = 1,024 sps vs. TA, Multiple VDD. FIGURE 2-22: IDD in Slow Mode vs. TA, Multiple VDD. FIGURE 2-23: IDD at ƒS = 8,192 sps vs. TA, Multiple VDD. FIGURE 2-24: IDD vs. TA, Multiple VDD, Multiple ƒS. FIGURE 2-25: IDD in Sleep Mode vs. TA, Multiple VDD. FIGURE 2-26: IDD in Power-down Mode vs. TA, Multiple VDD. FIGURE 2-27: ISENSE- vs. TA, Common Mode, Multiple VBUS. FIGURE 2-28: ISENSE+ vs. TA, Common Mode, Multiple VBUS. FIGURE 2-29: VSENSE- Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-30: VSENSE+ Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-31: IOL vs. VOL, TA = 25°C, VDD = 5.5V. FIGURE 2-32: ƒS Error across TA = -40°C to +125°C, n = 30,852 Total Samples. FIGURE 2-33: ƒS Error across TA = 30°C, n = 10,308 Total Samples. FIGURE 2-34: POR Threshold vs. TA. 3.0 Pin Descriptions TABLE 3-1: PAC1811 Pin Descriptions 3.1 Sense Voltage Pins (VSENSE+ and VSENSE–) 3.2 Ground Pin (GND) 3.3 Positive Power Supply Voltage Pin (VDD) 3.4 SMBus Data (SMBDAT) Pin (SDA) 3.5 SMBus Clock (SMBCLK) Pin (SCL) 3.6 A0 and A1 Multi-functional Pins 3.7 Power-down Pin (PWRDN) 3.8 Positive Bus Voltage Pin (VBUS+) 4.0 Device Description 4.1 Definitions 4.2 Detailed Description 4.3 Voltage Measurement EQUATION 4-1 4.4 Current Measurement 4.5 Selecting RSHUNT Values EQUATION 4-2 EQUATION 4-3 EQUATION 4-4 4.6 FSR/2 Modes TABLE 4-1: FSR/2 – VBUS TABLE 4-2: FSR/2 – VSENSE 4.7 ADC Measurements, Offset and Averaging 4.8 Power and Energy EQUATION 4-5 EQUATION 4-6 EQUATION 4-7 EQUATION 4-8 4.9 Conversion Cycles 4.10 Alert Functionality 5.0 SMBus and I2C Communications Protocols FIGURE 5-1: SMBus Timing Diagram. 5.1 Addressing and Control Bits TABLE 5-1: Address Select 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus and I2C Standard Protocol TABLE 5-2: Protocol Packet 5.5 Auto-incrementing Pointer FIGURE 5-2: READ and WRITE Auto-Incrementing Loops. 5.6 SMBus/I2C Commands TABLE 5-3: Refresh and Refresh_V Commands TABLE 5-4: General Call Response TABLE 5-5: Write Byte TABLE 5-6: Read Byte TABLE 5-7: Send Byte TABLE 5-8: Receive Byte TABLE 5-9: Block Write – I2C version TABLE 5-10: Block Read – I2C Version TABLE 5-11: Block Read – SMBus Version (Must set BYTE COUNT bit) 6.0 Register Description TABLE 6-1: PAC1811 Registers 6.1 Reading Data Bytes 6.2 Register Categories 6.3 Detailed Register Information Register 6-1: REFRESH (Address 00h) FIGURE 6-1: Host Read Period After a Refresh Command. Register 6-2: CONTROL (Address 01h) Register 6-3: ACC_COUNT (Address 02h) Register 6-4: VACC (Address 03h) Register 6-5: VBUS (Address 04h) Register 6-6: VSENSE (Address 05h) Register 6-7: VBUS_AVG (Address 06h) Register 6-8: VSENSE_AVG (Address 07h) Register 6-9: VPOWER (Address 08h) Register 6-10: VBUS_MIN (Address 09h) Register 6-11: VBUS_MAX (Address 0Ah) Register 6-12: VSENSE_MIN (Address 0Bh) Register 6-13: VSENSE_MAX (Address 0Ch) Register 6-14: VPOWER_MIN (Address 0Dh) Register 6-15: VPOWER_MAX (Address 0Eh) Register 6-16: CONTROL_LAT (Address 0Fh) Register 6-17: NEG_PWR_FSR_LAT (Address 10h) Register 6-18: ALERT_STATUS (Address 11h) Register 6-19: SMBUS_SETTINGS (Address 12h) Register 6-20: NEG_PWR_FSR (Address 13h) Register 6-21: REFRESH_G (Address 14h) Register 6-22: REFRESH_V (Address 15h) Register 6-23: SLOW (Address 16h) Register 6-24: CONTROL_ACT (Address 17h) Register 6-25: NEG_PWR_FSR_ACT (Address 18h) Register 6-26: SLOW_ALERT0 (Address 19h) Register 6-27: GPIO_ALERT1 (Address 1Ah) Register 6-28: ACC_FULL_LIMIT (Address 1BH) Register 6-29: OC_LIMIT (Address 1CH) Register 6-30: UC_LIMIT (Address 1DH) Register 6-31: OP_WARNING_LIMIT (Address 1EH) Register 6-32: OP_CRITICAL_LIMIT (Address 1FH) Register 6-33: OV_LIMIT (Address 20H) Register 6-34: UV_LIMIT (Address 21H) Register 6-35: STEP_LIMIT (Address 22H) Register 6-36: N-SAMPLES_LIMIT (Address 23h) Register 6-37: ALERT_ENABLE (Address 24h) Register 6-38: ACC_COUNT_PRESET (Address 25h) Register 6-39: VACC_PRESET (Address 26h) Register 6-40: PRODUCT_ID (Address FDh) Register 6-41: MANUFACTURER_ID (Address FEh) Register 6-42: REVISION_ID (Address FFh) 7.0 Packaging Information 7.1 Package Marking Information 7.2 Package Drawings Appendix A: Revision History Revision B (November 2025) Revision A (November 2025) Product Identification System Product Identification System (Automotive) Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature
Unless otherwise indicated, TA = -40°C to +125°C, VDD = 2.7V to 5.5V, VBUS = 0V to 42V, VSENSE = VSENSE+ – VSENSE– = 0V. 0.05 2
V = 3.3V V = 3.3V DD DD
0.025 0 0 -2
)
-0.025 -4 -0.05 -6
of Full Scale) Error (%
-0.075 -8
BUSV
-0.1
▬ T = -40°C A Error (%
-10
▬ T = 0°C ▬ T = -40°C A A
-0.125
▬ T = +25°C ▬ T = 0°C A A BUS ▬ T = +85°C ▬ T = +25°C A
-12
A V ▬ T = +125°C
-0.15
▬ T = +85°C A A ▬ T = +125°C A
-14 -0.175 0.01 0.1 1 10 0 5 10 15 20 25 30 35 40 45
V (V) BUS V (V) BUS FIGURE 2-13:
VBUS Error vs. VBUS,
FIGURE 2-16:
VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. Logarithmic Scale, Zoom View. 0.02 3000
V = 3.3V ▬ T = -40°C DD x = -6.07 μV A otal)
0.015
▬ T = 0°C σ = 2.29 μV A T ▬ T = +25°C
2500
LSBs = 1.5 μV A ▬ T = +85°C V = 10.5V BUS
0.01
A ▬ T = +125°C A
2000 0.005
of Full Scale)
1500 0
Samples (10,000
-0.005 1000
SENSEV Error (%
-0.01 500
BUSV
-0.015 0
Number of
3 -0.02 -9.16 -7.63 -6.10 -4.58 -3.05 -1.53 0.00 1.5 3.05 4.58 6.10 7.63 9.16 -5 0 5 10 15 20 25 30 35 40 45 -15.26 -13.73 -12.21 -10.68 10.68 12.21 13.73 15.26
V (V) V Offset (μV) BUS SENSE FIGURE 2-14:
VBUS Error vs. VBUS,
FIGURE 2-17:
VSENSE Offset Histogram, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. Bipolar FSR/2 Mode, n = 10,000 Total Samples, 8x Average. 0.03 3000
▬ T = -40°C x = -1.21 mV A V = 3.3V DD ▬ T = 0°C otal) σ = 1.03 mV A LSBs = 0.64 mV
0.02
▬ T = +25°C
2500
A V = 3.3V ▬ T = +85°C DD A ▬ T = +125°C A
2000 0.01
of Full Scale)
1500 0
Samples (10,000 T BUS
1000 -0.01
V Error (%
500
BUS
-0.02
V Number of
0 -0.03 -4 -1 2 5 2.6 3.2 3.8 4.4 5.6 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -6.4 -5.8 -5.2 -4.6 -3.4 -2.8 -2.2 -1.6 -0.4 0.2 0.8 1.4
V (V) V ADC Output (mV) BUS BUS FIGURE 2-15:
VBUS Error vs. VBUS,
FIGURE 2-18:
VBUS Offset Histogram, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Bipolar FSR/2 Mode, n = 10,000 Total Samples, Zoom View. 8x Average. 2025 Microchip Technology Inc. and its subsidiaries DS20007066B-page 9 Document Outline Single-Channel Power Monitor with Accumulator, 42V Full Scale Range Features Applications Description Package Types Functional Block Diagram 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings (†) FIGURE 1-1: PAC1811 ESD Protection Circuitry. 1.2 DC Electrical Specifications 1.3 AC Electrical Specifications 1.4 Temperature Specifications 2.0 Typical Performance Curves FIGURE 2-1: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Unipolar Mode. FIGURE 2-2: VSENSE Error vs. VSENSE, TA = 25°C, Multiple VDD, Bipolar FSR Mode. FIGURE 2-3: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode. FIGURE 2-4: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode. FIGURE 2-5: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode. FIGURE 2-6: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode. FIGURE 2-7: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-8: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-9: VSENSE Error vs. VSENSE, VDD = 5.5V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-10: VSENSE Error vs. VSENSE, VDD = 2.7V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-11: VBUS Error vs. VBUS, VDD = 3.3V, TA = 25°C, Unipolar Mode, Logarithmic Scale. FIGURE 2-12: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale. FIGURE 2-13: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Unipolar Mode, Logarithmic Scale, Zoom View. FIGURE 2-14: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-15: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode, Zoom View. FIGURE 2-16: VBUS Error vs. VBUS, VDD = 3.3V, Multiple TA, Bipolar FSR Mode. FIGURE 2-17: VSENSE Offset Histogram, Bipolar FSR/2 Mode, n = 10,000 Total Samples, 8x Average. FIGURE 2-18: VBUS Offset Histogram, Bipolar FSR/2 Mode, n = 10,000 Total Samples, 8x Average. FIGURE 2-19: VBUS Offset vs. TA, VDD = 3.3V, Bipolar FSR Mode. FIGURE 2-20: VSENSE DC Offset vs. TA, VBUS = 10.5V, Bipolar FSR Mode. FIGURE 2-21: IDD at ƒS = 1,024 sps vs. TA, Multiple VDD. FIGURE 2-22: IDD in Slow Mode vs. TA, Multiple VDD. FIGURE 2-23: IDD at ƒS = 8,192 sps vs. TA, Multiple VDD. FIGURE 2-24: IDD vs. TA, Multiple VDD, Multiple ƒS. FIGURE 2-25: IDD in Sleep Mode vs. TA, Multiple VDD. FIGURE 2-26: IDD in Power-down Mode vs. TA, Multiple VDD. FIGURE 2-27: ISENSE- vs. TA, Common Mode, Multiple VBUS. FIGURE 2-28: ISENSE+ vs. TA, Common Mode, Multiple VBUS. FIGURE 2-29: VSENSE- Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-30: VSENSE+ Leakage vs. TA, Common Mode, Multiple VBUS. FIGURE 2-31: IOL vs. VOL, TA = 25°C, VDD = 5.5V. FIGURE 2-32: ƒS Error across TA = -40°C to +125°C, n = 30,852 Total Samples. FIGURE 2-33: ƒS Error across TA = 30°C, n = 10,308 Total Samples. FIGURE 2-34: POR Threshold vs. TA. 3.0 Pin Descriptions TABLE 3-1: PAC1811 Pin Descriptions 3.1 Sense Voltage Pins (VSENSE+ and VSENSE–) 3.2 Ground Pin (GND) 3.3 Positive Power Supply Voltage Pin (VDD) 3.4 SMBus Data (SMBDAT) Pin (SDA) 3.5 SMBus Clock (SMBCLK) Pin (SCL) 3.6 A0 and A1 Multi-functional Pins 3.7 Power-down Pin (PWRDN) 3.8 Positive Bus Voltage Pin (VBUS+) 4.0 Device Description 4.1 Definitions 4.2 Detailed Description 4.3 Voltage Measurement EQUATION 4-1 4.4 Current Measurement 4.5 Selecting RSHUNT Values EQUATION 4-2 EQUATION 4-3 EQUATION 4-4 4.6 FSR/2 Modes TABLE 4-1: FSR/2 – VBUS TABLE 4-2: FSR/2 – VSENSE 4.7 ADC Measurements, Offset and Averaging 4.8 Power and Energy EQUATION 4-5 EQUATION 4-6 EQUATION 4-7 EQUATION 4-8 4.9 Conversion Cycles 4.10 Alert Functionality 5.0 SMBus and I2C Communications Protocols FIGURE 5-1: SMBus Timing Diagram. 5.1 Addressing and Control Bits TABLE 5-1: Address Select 5.2 SMBus Timeout 5.3 SMBus and I2C Compatibility 5.4 SMBus and I2C Standard Protocol TABLE 5-2: Protocol Packet 5.5 Auto-incrementing Pointer FIGURE 5-2: READ and WRITE Auto-Incrementing Loops. 5.6 SMBus/I2C Commands TABLE 5-3: Refresh and Refresh_V Commands TABLE 5-4: General Call Response TABLE 5-5: Write Byte TABLE 5-6: Read Byte TABLE 5-7: Send Byte TABLE 5-8: Receive Byte TABLE 5-9: Block Write – I2C version TABLE 5-10: Block Read – I2C Version TABLE 5-11: Block Read – SMBus Version (Must set BYTE COUNT bit) 6.0 Register Description TABLE 6-1: PAC1811 Registers 6.1 Reading Data Bytes 6.2 Register Categories 6.3 Detailed Register Information Register 6-1: REFRESH (Address 00h) FIGURE 6-1: Host Read Period After a Refresh Command. Register 6-2: CONTROL (Address 01h) Register 6-3: ACC_COUNT (Address 02h) Register 6-4: VACC (Address 03h) Register 6-5: VBUS (Address 04h) Register 6-6: VSENSE (Address 05h) Register 6-7: VBUS_AVG (Address 06h) Register 6-8: VSENSE_AVG (Address 07h) Register 6-9: VPOWER (Address 08h) Register 6-10: VBUS_MIN (Address 09h) Register 6-11: VBUS_MAX (Address 0Ah) Register 6-12: VSENSE_MIN (Address 0Bh) Register 6-13: VSENSE_MAX (Address 0Ch) Register 6-14: VPOWER_MIN (Address 0Dh) Register 6-15: VPOWER_MAX (Address 0Eh) Register 6-16: CONTROL_LAT (Address 0Fh) Register 6-17: NEG_PWR_FSR_LAT (Address 10h) Register 6-18: ALERT_STATUS (Address 11h) Register 6-19: SMBUS_SETTINGS (Address 12h) Register 6-20: NEG_PWR_FSR (Address 13h) Register 6-21: REFRESH_G (Address 14h) Register 6-22: REFRESH_V (Address 15h) Register 6-23: SLOW (Address 16h) Register 6-24: CONTROL_ACT (Address 17h) Register 6-25: NEG_PWR_FSR_ACT (Address 18h) Register 6-26: SLOW_ALERT0 (Address 19h) Register 6-27: GPIO_ALERT1 (Address 1Ah) Register 6-28: ACC_FULL_LIMIT (Address 1BH) Register 6-29: OC_LIMIT (Address 1CH) Register 6-30: UC_LIMIT (Address 1DH) Register 6-31: OP_WARNING_LIMIT (Address 1EH) Register 6-32: OP_CRITICAL_LIMIT (Address 1FH) Register 6-33: OV_LIMIT (Address 20H) Register 6-34: UV_LIMIT (Address 21H) Register 6-35: STEP_LIMIT (Address 22H) Register 6-36: N-SAMPLES_LIMIT (Address 23h) Register 6-37: ALERT_ENABLE (Address 24h) Register 6-38: ACC_COUNT_PRESET (Address 25h) Register 6-39: VACC_PRESET (Address 26h) Register 6-40: PRODUCT_ID (Address FDh) Register 6-41: MANUFACTURER_ID (Address FEh) Register 6-42: REVISION_ID (Address FFh) 7.0 Packaging Information 7.1 Package Marking Information 7.2 Package Drawings Appendix A: Revision History Revision B (November 2025) Revision A (November 2025) Product Identification System Product Identification System (Automotive) Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature