Datasheet LTC7893 (Analog Devices) - 10

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Data Sheet LTC7893
to 1.2V. Connect VPRG to INTVCC or GND to program the output to 28V or 24V, respectively, through an internal resistor divider on VFB. 7 VBIAS Main Supply Pin. A bypass capacitor must be tied between VBIAS and GND. Gate Driver Power Supply Pin. The gate drivers are powered from DRV 8 DRV CC. Connect CC DRVCC to INTVCC by a separate trace to the INTVCC bypass capacitor. Bootstrap diode anode connection pin. An optional external Schottky diode can be 9 BSTVCC placed between the BSTVCC and BOOST pins to bypass most of the 7Ω switch resistance between DRVCC and BOOST. External Power Input to an Internal LDO Regulator Connected to DRVCC. This LDO regulator supplies INTVCC power, bypassing the internal VBIAS LDO regulator whenever EXTV 10 EXTV CC is higher than the EXTVCC switchover voltage. See the EXTVCC connection in the CC Power and Bias Supplies (VBIAS, EXTVCC, DRVCC, and INTVCC) section and INTVCC Regulators (OPTI-DRIVE) section. Do not exceed 30V on EXTVCC. Connect EXTVCC to GND if the EXTVCC LDO regulator is not used. Output of the Internal LDO Regulator. The INTVCC voltage regulation point is set by the 11 INTVCC DRVSET pin. INTVCC must be decoupled to GND with a 4.7μF to 10μF ceramic or other low equivalent series resistance (ESR) capacitor. High Current Gate Driver Pull-Up for Bottom FET. BGUP pulls up to DRVCC. Tie BGUP directly to the bottom FET gate for maximum gate drive transition speed on the gate 12 BGUP rising edge. Tie a resistor between BGUP and the bottom FET gate to adjust the gate rising slew rate. BGUP also serves as the Kelvin sense of the bottom FET gate during turn off. High Current Gate Driver Pull-Down for Bottom FET. BGDN pulls down to GND. Tie BGDN directly to the bottom FET gate for maximum gate drive transition speed on the 13 BGDN gate falling edge. Tie a resistor between BGDN and the bottom FET gate to adjust the gate falling slew rate. BGDN also serves as the Kelvin sense of the bottom FET gate during turn on. Bootstrapped Supply to the Top Side Floating Driver. Connect a capacitor between the BOOST and SW pins. An internal switch provides power to the BOOST pin from DRV 14 BOOST CC when the bottom FET turns on. The voltage swing at the BOOST pin is from DRVCC to (VOUT + DRVCC). 15 SW Switch Node Connection to Inductor. High Current Gate Driver Pull-Down for Top FET. TGDN pulls down to SW. Tie TGDN directly to the top FET gate for maximum gate drive transition speed on the gate falling 16 TGDN edge. Tie a resistor between TGDN and the top FET gate to adjust the gate falling slew rate. High Current Gate Driver Pull-Up for Top FET. TGUP pulls up to BOOST. Tie TGUP directly to the top FET gate for maximum gate drive transition speed on the gate rising 17 TGUP edge. Tie a resistor between TGUP and the top FET gate to adjust the gate rising slew rate. Power Good Open-Drain Logic Output. PGOOD is pulled to GND when the voltage on 18 PGOOD VFB is not within ±10% of its set point.
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Rev. 0 10 of 48 Document Outline Features Applications General Description Typical Application TABLE OF CONTENTS Revision History Specifications Absolute Maximum Ratings Pin Configurations and Function Descriptions Typical Performance Characteristics Functional diagram Theory of Operation Main Control Loop Power and Bias Supplies (VBIAS, EXTVCC, DRVCC, and INTVCC) High-Side Bootstrap Capacitor Dead Time Control (DTCA and DTCB Pins) Startup and Shutdown (RUN and SS Pins) Light Load Operation: Burst Mode Operation, Pulse-Skipping, or Forced Continuous Mode (MODE Pin) Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and PLLIN/SPREAD Pins) Output Overvoltage Protection Power Good Applications Information Inductor Value Calculation Inductor Core Selection Current Sense Selection Low Value Resistor Current Sensing Inductor DCR Current Sensing Setting the Operating Frequency Selecting the Light-Load Operating Mode Dead Time Control (DTCA and DTCB Pins) DTCx Pin Tied to Ground (Adaptive Dead Time Control) DTCx Pin connected with a resistor to GND Power FET Selection CIN and COUT Selection Setting the Output Voltage RUN Pin and Undervoltage Lockout Soft-Start (SS Pin) INTVCC Regulators (OPTI-DRIVE) Topside FET Driver Supply (CB) Minimum On-Time Considerations Fault Conditions: Overtemperature Protection Phase-Locked Loop and Frequency Synchronization Efficiency Considerations Checking Transient Response Design Example PCB Board Layout Checklist PCB Layout Debugging Typical Applications Related Parts Outline Dimensions Ordering Guide