Datasheet UCC34141-Q1 (Texas Instruments) - 4

link to page 5
UCC34141-Q1
SLUSFP1D – APRIL 2024 – REVISED APRIL 2026
www.ti.com 5 Pin Configuration and Functions
PG (PG)
Figure 5-1. DHA Package, 16-Pin SSOP (Top View) Table 5-1. Pin Functions PIN TYPE
(1)
DESCRIPTION NAME NO.
Internal buck-boost converter switch pin. Connect an inductor from this pin to COM. Recommend BSW 13 P a 3.3µH to 10µH chip inductor. If using the device in single output mode leave this pin floating. COM 10, 11 G Secondary ground. Connect to Source of power switch. Secondary-side analog sense reference connection for the noise sensitive analog feedback input FBVDD, and FBVEE. Connect the low-side FBVDD feedback resistor and high frequency COMA 9 G decoupling filter capacitors close to the COMA pin and respective feedback pin FBVDD. Connect to secondary-side gate drive voltage reference, COM. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the COMA pin. Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device ENA 1 I functionality. Can be used to program input UVLO with a resistor divider from VIN. Feedback (VDD – COM) output voltage sense pin and to adjust the output (VDD – COM) voltage. Connect a resistor divider from VDD to COMA so that the midpoint is connected to FBVDD. The equivalent FBVDD voltage is regulated at 2.5V with the internal hysteresis control across isolation. FBVDD 15 I Adding a 470pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor is needed. The 470pF ceramic capacitor for high frequency bypass must be next to the FBVDD and COMA pins on top layer or back layer connected with vias. Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect one feedback resistor to VEE to program the (COM – VEE) voltage from 2V to 8V. FBVEE 16 I Connect a 10pF ceramic capacitor from FBVEE to COMA for bypassing high frequency noise. The 10pF ceramic capacitor must be next to the FBVEE pin on top layer or back layer connected with vias. If using the device in single output mode connect a 180kΩ resistor to VEE. GNDP 5, 6, 7, 8 G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. Power-Good open-drain output pin. Remains active when VVIN_UVLOP ≤ VVIN ≤ VVIN_OVLOP; VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP; VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP; TJ_Primary ≤ TSHUT_P_R; and T PG(PG) 2 O J_secondary ≤ TSHUT_S_R. Pull up to a 3.3V or 5V rail through a 4.99kΩ resistor. Connect a 1uF decoupling capacitor in 0402 body size for by-passing the high frequency noise next to the Power-Good pin on the same side of the PCB as the IC. This pin is active low for UCC34141-Q1 but can active high depending on the part number. Secondary-side isolated output voltage from transformer. Connect a 10µF and a parallel 0.1µF VDD 12 P ceramic capacitor from VDD to COM. The 0.1µF ceramic capacitor in 0402 body size is for bypassing high frequency noise and must be next to the VDD and COM pins. Secondary-side isolated output voltage for negative rail. Connect a 2.2µF ceramic capacitor from VEE 14 P VEE to COM for bypassing high frequency noise. If using the device in single output mode connect VEE directly to COM. 4 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: UCC34141-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Device Comparison 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Insulation Specifications 6.6 Electrical Characteristics 6.7 Safety Limiting Values 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Power Stage Operation 7.3.1.1 VDD-COM Voltage Regulation 7.3.1.2 COM-VEE Voltage Regulation 7.3.1.3 COM-VEE Output Capability 7.3.2 Output Voltage Soft Start 7.3.3 ENA and Power-Good 7.3.4 Protection Functions 7.3.4.1 Input Undervoltage Lockout 7.3.4.2 Input Overvoltage Lockout 7.3.4.3 Output Undervoltage Protection 7.3.4.4 Output Overvoltage Protection 7.3.4.5 Output Short Circuit Protection 7.3.4.6 Over-Temperature Protection 7.3.4.7 BSW Pin Faults Protection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.2.1 VDD-COM Voltage Regulation 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration 8.3 System Examples 8.4 Power Supply Recommendations 8.5 Layout 8.5.1 Layout Guidelines 8.5.2 Layout Example 9 Device and Documentation Support 9.1 Third-Party Products Disclaimer 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information