Datasheet dsPIC33CK256MC006 (Microchip) - 3

dsPIC33CK256MC006 Family
• Two Four-Wire SPI/I2S Modules: – 16-byte FIFO – Variable width – I2S mode • One CAN Flexible Data (FD) Module • One I2C Module with SMBus Support • PPS to Allow Function Remap • Programmable Cyclic Redundancy Check (CRC) • One SENT Module
Direct Memory Access (DMA)
• Four DMA Channels
Peripheral Features
• High-Current I/O Sink/Source • Edge or Level Change Notification Interrupt on I/O Pins • Peripheral Pin Select (PPS) Remappable Pins
Debugger Development Support
• In-Circuit and In-Application Programming • Three Complex, Five Simple Breakpoints • IEEE 1149.2 Compatible (JTAG) Boundary Scan • Trace Buffer and Run-Time Watch
Safety Features
• Backup Fast RC Oscillator (BFRC) • Brown-out Reset (BOR) • Capless Internal Voltage Regulator • Clock Monitor System with Backup Oscillator • CodeGuard™ Security • Cyclic Redundancy Check (CRC) • Dual Watchdog Timer (WDT) • Fail-Safe Clock Monitoring (FSCM) • Flash Error Correcting Code (ECC) • Flash OTP by ICSP™ Write Inhibit • RAM Memory Built-In Self-Test (MBIST) • Two-Speed Start-up • Virtual Pins for Redundancy and Monitoring • Windowed Deadman Timer (DMT)  Data Sheet DS70005633B - 3 © 2026 Microchip Technology Inc. and its subsidiaries Document Outline Operating Conditions Core: 16-Bit dsPIC33CK CPU Clock Management Power Management High-Speed PWM Timers/Output Compare/Input Capture Advanced Analog Features Communication Interfaces Direct Memory Access (DMA) Peripheral Features Debugger Development Support Safety Features Qualification Support dsPIC33CK256MC006 Product Families Pin Diagrams Pin Diagrams (Continued) Pin Diagrams (Continued) Pin Diagrams (Continued) Table of Contents 1.  Device Overview 2.  Guidelines for Getting Started with 16-Bit Digital Signal Controllers 2.1.  Basic Connection Requirements 2.2.  Decoupling Capacitors 2.3.  Master Clear (MCLR) Pin 2.4.  ICSP Pins 2.5.  External Oscillator Pins 2.6.  External Oscillator Layout Guidance 2.7.  Oscillator Value Conditions on Device Start-up 2.8.  Unused I/Os 2.9.  Bulk Capacitors 2.10.  Targeted Applications 3.  CPU 3.1.  Registers 3.2.  Instruction Set 3.3.  Data Space Addressing 3.4.  Addressing Modes 3.4.1.  Programmer’s Model 3.4.2.  CPU Resources 3.4.2.1.  Key Resources 3.5.  CPU Control/Status Registers 3.5.1.  Working Register x 3.5.2.  Stack Pointer Limit Value Register 3.5.3.  Accumulator A Low Register 3.5.4.  Accumulator A High Register 3.5.5.  Accumulator A Upper Register 3.5.6.  Accumulator B Low Register 3.5.7.  Accumulator B High Register 3.5.8.  Accumulator B Upper Address Register 3.5.9.  Program Counter Low Register 3.5.10.  Program Counter High Register 3.5.11.  Data Space Read Page Register 3.5.12.  Data Space Write Page Register 3.5.13.  REPEAT Loop Counter Register 3.5.14.  DO Loop Iteration Count Register 3.5.15.  DO Loop Start Address Register Low 3.5.16.  DO Loop Start Address Register High 3.5.17.  DO Loop End Address Register Low 3.5.18.  DO Loop End Address Register High 3.5.19.  CPU STATUS Register 3.5.20.  Core Control Register 3.5.21.  Modulo and Bit-Reversed Addressing Control Register 3.5.22.  X AGU Modulo Addressing Start Register 3.5.23.  X AGU Modulo Addressing End Register 3.5.24.  Y AGU Modulo Addressing Start Register 3.5.25.  Y AGU Modulo Addressing End Register 3.5.26.  X AGU Bit-Reversed Addressing Control Register 3.5.27.  Disable Interrupt Count Register 3.5.28.  Table Memory Page Address Register 3.5.29.  Y Page Register 3.5.30.  EDS Bus Master Priority Control Register 3.5.31.  CPU W Register Context Status Register 3.6.  Arithmetic Logic Unit (ALU) 3.6.1.  Multiplier 3.6.2.  Divider 3.7.  DSP Engine 4.  Memory Organization 4.1.  Program Address Space 4.1.1.  Program Memory Organization 4.1.2.  Interrupt and Trap Vectors 4.1.3.  Unique Device Identifier (UDID) 4.2.  Data Address Space 4.2.1.  Data Space Width 4.2.2.  Data Memory Organization and Alignment 4.2.3.  SFR Space 4.2.4.  Near Data Space 4.2.5.  X and Y Data Spaces 4.3.  BIST Overview 4.3.1.  BIST at Start-up 4.3.2.  BIST at Run Time 4.3.2.1.  Fault Simulation 4.3.3.  MBIST Control Register 4.4.  Memory Resources 4.4.1.  Key Resources 4.4.2.  Paged Memory Scheme 4.4.2.1.  Extended X Data Space 4.4.2.2.  Software Stack 4.4.3.  Instruction Addressing Modes 4.4.3.1.  File Registration Instructions 4.4.3.2.  MCU Instructions 4.4.3.3.  Move and Accumulator Instructions 4.4.3.4.  MAC Instructions 4.4.3.5.  Other Instructions 4.4.4.  Modulo Addressing 4.4.4.1.  Modulo and Bit-Reversed Addressing Control Register 4.4.4.2.  X AGU Modulo Addressing Start Register 4.4.4.3.  X AGU Modulo Addressing End Register 4.4.4.4.  Y AGU Modulo Addressing Start Register 4.4.4.5.  Y AGU Modulo Addressing End Register 4.4.4.6.  X AGU Bit-Reversed Addressing Control Register 4.4.4.7.  Start and End Address 4.4.4.8.  W Address Register Selection 4.4.4.9.  Modulo Addressing Applicability 4.5.  Bit-Reversed Addressing 4.5.1.  Bit-Reversed Addressing Implementation 4.6.  Interfacing Program and Data Memory Spaces 4.6.1.  Data Access from Program Memory Using Table Instructions 5.  Flash Program Memory 5.1.  Table Instructions and Flash Programming 5.2.  RTSP Operation 5.3.  Error Correcting Code (ECC) 5.4.  ECC Fault Injection 5.5.  Flash OTP by ICSP™ Write Inhibit 5.5.1.  Activating Flash OTP by ISCP Write Inhibit 5.6.  Program Flash Memory Control Registers 5.6.1.  NVM Control Registers 5.6.1.1.  Nonvolatile Memory (NVM) Control Register 5.6.1.2.  Nonvolatile Memory Lower Address Register 5.6.1.3.  Nonvolatile Memory Upper Address Register 5.6.1.4.  Nonvolatile Memory Key Register 5.6.1.5.  NVM Source Data Address Register Low 5.6.1.6.  NVM Source Data Address Register High 5.7.  ECC Control Registers 5.7.1.  ECC Fault Injection Configuration Register Low 5.7.2.  ECC Fault Injection Configuration Register High 5.7.3.  ECC Fault Inject Address Compare Register Low 5.7.4.  ECC Fault Inject Address Compare Register High 5.7.5.  ECC System Status Display Register Low 5.7.6.  ECC System Status Display Register High 6.  Resets 6.1.  Reset Resources 6.2.  Reset Control Register 6.3.  Key Resources 7.  Interrupt Controller 7.1.  Interrupt Vector Table 7.2.  Alternate Interrupt Vector Table 7.3.  Reset Sequence 7.4.  Interrupt Resources 7.4.1.  Key Resources 7.5.  Interrupt Control and Status Registers 7.6.  INTCON1 through INTCON4 7.6.1.  IFSx 7.6.2.  IECx 7.6.3.  IPCx 7.6.4.  INTTREG 7.7.  Status/Control Registers 7.7.1.  Interrupt Request Flags Register 0 7.7.2.  Interrupt Request Flags Register 1 7.7.3.  Interrupt Request Flags Register 2 7.7.4.  Interrupt Request Flags Register 3 7.7.5.  Interrupt Request Flags Register 4 7.7.6.  Interrupt Request Flags Register 5 7.7.7.  Interrupt Request Flags Register 6 7.7.8.  Interrupt Request Flags Register 7 7.7.9.  Interrupt Request Flags Register 10 7.7.10.  Interrupt Request Flags Register 11 7.7.11.  Interrupt Enable Register 0 7.7.12.  Interrupt Enable Register 1 7.7.13.  Interrupt Enable Register 2 7.7.14.  Interrupt Enable Register 3 7.7.15.  Interrupt Enable Register 4 7.7.16.  Interrupt Enable Register 5 7.7.17.  Interrupt Enable Register 6 7.7.18.  Interrupt Enable Register 7 7.7.19.  Interrupt Enable Register 10 7.7.20.  Interrupt Enable Register 11 7.7.21.  Interrupt Priority Register 0 7.7.22.  Interrupt Priority Register 1 7.7.23.  Interrupt Priority Register 2 7.7.24.  Interrupt Priority Register 3 7.7.25.  Interrupt Priority Register 4 7.7.26.  Interrupt Priority Register 5 7.7.27.  Interrupt Priority Register 6 7.7.28.  Interrupt Priority Register 7 7.7.29.  Interrupt Priority Register 8 7.7.30.  Interrupt Priority Register 9 7.7.31.  Interrupt Priority Register 10 7.7.32.  Interrupt Priority Register 11 7.7.33.  Interrupt Priority Register 12 7.7.34.  Interrupt Priority Register 13 7.7.35.  Interrupt Priority Register 14 7.7.36.  Interrupt Priority Register 15 7.7.37.  Interrupt Priority Register 16 7.7.38.  Interrupt Priority Register 17 7.7.39.  Interrupt Priority Register 18 7.7.40.  Interrupt Priority Register 19 7.7.41.  Interrupt Priority Register 20 7.7.42.  Interrupt Priority Register 21 7.7.43.  Interrupt Priority Register 22 7.7.44.  Interrupt Priority Register 23 7.7.45.  Interrupt Priority Register 24 7.7.46.  Interrupt Priority Register 25 7.7.47.  Interrupt Priority Register 26 7.7.48.  Interrupt Priority Register 27 7.7.49.  Interrupt Priority Register 28 7.7.50.  Interrupt Priority Register 29 7.7.51.  Interrupt Priority Register 30 7.7.52.  Interrupt Priority Register 31 7.7.53.  Interrupt Priority Register 42 7.7.54.  Interrupt Priority Register 43 7.7.55.  Interrupt Priority Register 44 7.7.56.  Interrupt Priority Register 45 7.7.57.  Interrupt Priority Register 47 7.7.58.  Interrupt Control Register 1 7.7.59.  Interrupt Control Register 2 7.7.60.  Interrupt Control Register 3 7.7.61.  Interrupt Control Register 4 7.7.62.  Interrupt Control and Status Register 7.8.  Key Resources 8.  I/O Ports 8.1.  Parallel I/O (PIO) Ports 8.1.1.  Open-Drain Configuration 8.2.  Configuring Analog and Digital Port Pins 8.2.1.  I/O Port Write/Read Timing 8.2.2.  Port Controls/Status Registers 8.2.2.1.  Analog Select for PORTA Register 8.2.2.2.  Output Enable for PORTA Register 8.2.2.3.  Input Data for PORTA Register 8.2.2.4.  Output Data for PORTA Register 8.2.2.5.  Open-Drain Enable for PORTA Register 8.2.2.6.  Change Notification Pull-up Enable for PORTA Register 8.2.2.7.  Change Notification Pull-Down Enable for PORTA Register 8.2.2.8.  Change Notification Control for PORTA Register 8.2.2.9.  Interrupt Change Notification Enable for PORTA Register 8.2.2.10.  Interrupt Change Notification Status for PORTA Register 8.2.2.11.  Interrupt Change Notification Edge Select for PORTA Register 8.2.2.12.  Interrupt Change Notification Flag for PORTA Register 8.2.2.13.  Analog Select for PORTB Register 8.2.2.14.  Output Enable for PORTB Register 8.2.2.15.  Input Data for PORTB Register 8.2.2.16.  Output Data for PORTB Register 8.2.2.17.  Open-Drain Enable for PORTB Register 8.2.2.18.  Change Notification Pull-up Enable for PORTB Register 8.2.2.19.  Change Notification Pull-Down Enable for PORTB Register 8.2.2.20.  Change Notification Control for PORTB Register 8.2.2.21.  Interrupt Change Notification Enable for PORTB Register 8.2.2.22.  Interrupt Change Notification Status for PORTB Register 8.2.2.23.  Interrupt Change Notification Edge Select for PORTB Register 8.2.2.24.  Interrupt Change Notification Flag for PORTB Register 8.2.2.25.  Analog Select for PORTC Register 8.2.2.26.  Output Enable for PORTC Register 8.2.2.27.  Input Data for PORTC Register 8.2.2.28.  Output Data for PORTC Register 8.2.2.29.  Open-Drain Enable for PORTC Register 8.2.2.30.  Change Notification Pull-up Enable for PORTC Register 8.2.2.31.  Change Notification Pull-Down Enable for PORTC Register 8.2.2.32.  Change Notification Control for PORTC Register 8.2.2.33.  Interrupt Change Notification Enable for PORTC Register 8.2.2.34.  Interrupt Change Notification Status for PORTC Register 8.2.2.35.  Interrupt Change Notification Edge Select for PORTC Register 8.2.2.36.  Interrupt Change Notification Flag for PORTC Register 8.2.2.37.  Analog Select for PORTD Register 8.2.2.38.  Output Enable for PORTD Register 8.2.2.39.  Input Data for PORTD Register 8.2.2.40.  Output Data for PORTD Register 8.2.2.41.  Open-Drain Enable for PORTD Register 8.2.2.42.  Change Notification Pull-up Enable for PORTD Register 8.2.2.43.  Change Notification Pull-Down Enable for PORTD Register 8.2.2.44.  Change Notification Control for PORTD Register 8.2.2.45.  Interrupt Change Notification Enable for PORTD Register 8.2.2.46.  Interrupt Change Notification Status for PORTD Register 8.2.2.47.  Interrupt Change Notification Edge Select for PORTD Register 8.2.2.48.  Interrupt Change Notification Flag for PORTD Register 8.3.  Input Change Notification (ICN) 8.4.  Peripheral Pin Select (PPS) 8.4.1.  Available Pins 8.4.2.  Available Peripherals 8.4.3.  Controlling Configuration Changes 8.4.3.1.  Control Register Lock 8.5.  Considerations for Peripheral Pin Selection 8.6.  Input Mapping 8.7.  Virtual Connections 8.8.  Output Mapping 8.9.  Mapping Limitations 8.10.  I/O Helpful Tips 8.11.  I/O Ports Resources 8.11.1.  Key Resources 8.11.2.  Peripheral Pin Select Control Registers 8.11.2.1.  Peripheral Remapping Configuration Register 8.11.2.2.  Peripheral Pin Select Input Register 0 8.11.2.3.  Peripheral Pin Select Input Register 1 8.11.2.4.  Peripheral Pin Select Input Register 2 8.11.2.5.  Peripheral Pin Select Input Register 3 8.11.2.6.  Peripheral Pin Select Input Register 4 8.11.2.7.  Peripheral Pin Select Input Register 5 8.11.2.8.  Peripheral Pin Select Input Register 6 8.11.2.9.  Peripheral Pin Select Input Register 11 8.11.2.10.  Peripheral Pin Select Input Register 12 8.11.2.11.  Peripheral Pin Select Input Register 13 8.11.2.12.  Peripheral Pin Select Input Register 18 8.11.2.13.  Peripheral Pin Select Input Register 19 8.11.2.14.  Peripheral Pin Select Input Register 20 8.11.2.15.  Peripheral Pin Select Input Register 21 8.11.2.16.  Peripheral Pin Select Input Register 22 8.11.2.17.  Peripheral Pin Select Input Register 23 8.11.2.18.  Peripheral Pin Select Input Register 26 8.11.2.19.  Peripheral Pin Select Input Register 27 8.11.2.20.  Peripheral Pin Select Input Register 37 8.11.2.21.  Peripheral Pin Select Input Register 38 8.11.2.22.  Peripheral Pin Select Input Register 42 8.11.2.23.  Peripheral Pin Select Input Register 43 8.11.2.24.  Peripheral Pin Select Input Register 44 8.11.2.25.  Peripheral Pin Select Input Register 45 8.11.2.26.  Peripheral Pin Select Input Register 46 8.11.2.27.  Peripheral Pin Select Input Register 47 8.11.2.28.  Peripheral Pin Select Input Register 48 8.11.2.29.  Peripheral Pin Select Input Register 49 8.11.2.30.  Peripheral Pin Select Output Register 0 8.11.2.31.  Peripheral Pin Select Output Register 1 8.11.2.32.  Peripheral Pin Select Output Register 2 8.11.2.33.  Peripheral Pin Select Output Register 3 8.11.2.34.  Peripheral Pin Select Output Register 4 8.11.2.35.  Peripheral Pin Select Output Register 5 8.11.2.36.  Peripheral Pin Select Output Register 6 8.11.2.37.  Peripheral Pin Select Output Register 7 8.11.2.38.  Peripheral Pin Select Output Register 8 8.11.2.39.  Peripheral Pin Select Output Register 9 8.11.2.40.  Peripheral Pin Select Output Register 10 8.11.2.41.  Peripheral Pin Select Output Register 11 8.11.2.42.  Peripheral Pin Select Output Register 12 8.11.2.43.  Peripheral Pin Select Output Register 13 8.11.2.44.  Peripheral Pin Select Output Register 14 8.11.2.45.  Peripheral Pin Select Output Register 15 8.11.2.46.  Peripheral Pin Select Output Register 16 8.11.2.47.  Peripheral Pin Select Output Register 17 8.11.2.48.  Peripheral Pin Select Output Register 18 8.11.2.49.  Peripheral Pin Select Output Register 19 8.11.2.50.  Peripheral Pin Select Output Register 20 8.11.2.51.  Peripheral Pin Select Output Register 21 8.11.2.52.  Peripheral Pin Select Output Register 22 8.11.2.53.  Peripheral Pin Select Output Register 23 8.11.2.54.  Peripheral Pin Select Output Register 24 8.11.2.55.  Peripheral Pin Select Output Register 25 8.11.2.56.  Peripheral Pin Select Output Register 26 9.  Oscillator with High-Frequency PLL 9.1.  Primary PLL 9.2.  CPU Clocking 9.3.  Primary Oscillator (POSC) 9.3.1.  Primary Oscillator Pin Functionality 9.4.  Internal Fast RC (FRC) Oscillator 9.5.  Low-Power RC (LPRC) Oscillator 9.6.  Internal Backup Fast RC (BFRC) Oscillator 9.7.  Reference Clock Output 9.8.  Oscillator Configuration 9.9.  OSCCON Unlock Sequence 9.10.  Oscillator Control Registers 9.10.1.  Oscillator Control Register 9.10.2.  Clock Divider Register 9.10.3.  PLL Feedback Divider Register 9.10.4.  PLL Output Divider Register 9.10.5.  FRC Oscillator Tuning Register 9.10.6.  CAN Clock Control Register 9.10.7.  Reference Clock Control Low Register 9.10.8.  Reference Clock Control High Register 9.10.9.  Reference Clock Trim Register 10.  Direct Memory Access (DMA) Controller 10.1.  Summary of DMA Operations 10.1.1.  Source and Destination 10.1.2.  Data Size 10.1.3.  Trigger Source 10.1.4.  Transfer Mode 10.1.5.  Addressing Modes 10.1.6.  Channel Priority 10.2.  Typical Setup 10.2.1.  Peripheral Module Disable 10.2.2.  DMA Registers 10.2.3.  DMA Control Registers 10.2.3.1.  DMA Engine Control Register 10.2.3.2.  DMA Buffer Register 10.2.3.3.  DMA Low Address Limit Register 10.2.3.4.  DMA High Address Limit Register 10.2.3.5.  DMA Channel n Control Register 10.2.3.6.  DMA Channel n Interrupt Register 10.2.3.7.  DMA Data Source Address Pointer Channel n Register 10.2.3.8.  DMA Data Source Address Pointer Channel n Register 10.2.3.9.  DMA Transaction Counter Channel n Register 10.2.4.  DMA Trigger Sources 11.  Controller Area Network Flexible Data-Rate (CAN FD) Modules 11.1.  Features 11.2.  CAN Control/Status Registers 11.2.1.  CAN Control Register Low 11.2.2.  CAN Control Register High 11.2.3.  CAN Nominal Bit Time Configuration Register Low 11.2.4.  CAN Nominal Bit Time Configuration Register High 11.2.5.  CAN Data Bit Time Configuration Register Low 11.2.6.  CAN Data Bit Time Configuration Register High 11.2.7.  CAN Transmitter Delay Compensation Register Low 11.2.8.  CAN Transmitter Delay Compensation Register High 11.2.9.  CAN Time Base Counter Register Low 11.2.10.  CAN Time Base Counter Register High 11.2.11.  CAN Timestamp Control Register Low 11.2.12.  CAN Timestamp Control Register High 11.2.13.  CAN Interrupt Code Register Low 11.2.14.  CAN Interrupt Code Register High 11.2.15.  CAN Interrupt Register Low 11.2.16.  CAN Interrupt Register High 11.2.17.  CAN Receive Interrupt Status Register Low 11.2.18.  CAN Receive Interrupt Status Register High 11.2.19.  CAN Transmit Interrupt Status Register 11.2.20.  CAN Transmit Interrupt Status Register High 11.2.21.  CAN Receive Overflow Interrupt Status Register Low 11.2.22.  CAN Receive Overflow Interrupt Status Register High 11.2.23.  CAN Transmit Attempt Interrupt Status Register Low 11.2.24.  CAN Transmit Attempt Interrupt Status Register High 11.2.25.  CAN Transmit Request Register Low 11.2.26.  CAN Transmit Request Register High 11.2.27.  CAN Transmit/Receive Error Count Register Low 11.2.28.  CAN Transmit/receive Error Count Register High 11.2.29.  CAN Bus Diagnostics Register 0 Low 11.2.30.  CAN Bus Diagnostics Register 0 High 11.2.31.  CAN Bus Diagnostics Register 1 Low 11.2.32.  CAN Bus Diagnostics Register 1 High 11.2.33.  CAN Transmit Event FIFO Control Register Low 11.2.34.  CAN Transmit Event FIFO Control Register High 11.2.35.  CAN Transmit Event FIFO Status Register 11.2.36.  CAN Transmit Event FIFO User Address Register Low 11.2.37.  CAN Transmit Event FIFO User Address Register High 11.2.38.  CAN Message Memory Base Address Register Low 11.2.39.  CAN Message Memory Base Address Register High 11.2.40.  CAN Transmit Queue Control Register Low 11.2.41.  CAN Transmit Queue Control Register High 11.2.42.  CAN Transmit Queue Status Register 11.2.43.  CAN Transmit Queue User Address Register Low 11.2.44.  CAN Transmit Queue User Address Register High 11.2.45.  CAN FIFO Control Register x Low (x = 1 to 8) 11.2.46.  CAN FIFO Control Register x High (x = 1 to 8) 11.2.47.  CAN FIFO Status Register x (x = 1 to 8) 11.2.48.  CAN FIFO User Address Register x Low (x = 1 to 8) 11.2.49.  CAN FIFO User Address Register x High (x = 1 to 8) 11.2.50.  CAN Filter Control Register x Low (x = 0 to 3) 11.2.51.  CAN Filter Control Register x High (x = 0 to 3) 11.2.52.  CAN Filter Object Register x Low (x = 0 to 15) 11.2.53.  CAN Filter Object Register x High (x = 0 to 15) 11.2.54.  CAN Mask Register x Low (x = 0 to 15) 11.2.55.  CAN Mask Register x High (x = 0 to 15) 12.  High-Speed PWM 12.1.  Features 12.2.  Architecture Overview 12.3.  Lock and Write Restrictions 12.4.  PWM4H/L Output on Peripheral Pin Select 12.5.  PWM Control/Status Registers 12.6.  Control Registers 12.6.1.  PWM Clock Control Register 12.6.2.  Frequency Scale Register 12.6.3.  Frequency Scaling Minimum Period Register 12.6.4.  Master Phase Register 12.6.5.  Master Duty Cycle Register 12.6.6.  Master Period Register 12.6.7.  Linear Feedback Shift Register 12.6.8.  Combinatorial Trigger Register Low 12.6.9.  Combinatorial Trigger Register High 12.6.10.  Combinatorial PWM Logic Control Register y 12.6.11.  PWM Event Output Control Register y 12.6.12.  PWM Generator x Control Register Low 12.6.13.  PWM Generator x Control Register High 12.6.14.  PWM Generator x Status Register 12.6.15.  PWM Generator x I/O Control Register Low 12.6.16.  PWM Generator x I/O Control Register High 12.6.17.  PWM Generator x Event Register Low 12.6.18.  PWM Generator x Event Register High 12.6.19.  PWM Generator x PCI Register Low 12.6.20.  PWM Generator x PCI Register High 12.6.21.  PWM Generator x PCI Register Low 12.6.22.  PWM Generator x PCI Register High 12.6.23.  PWM Generator x Leading-Edge Blanking Register Low 12.6.24.  PWM Generator x Leading-Edge Blanking Register High 12.6.25.  PWM Generator x PCI Register Low 12.6.26.  PWM Generator x PCI Register High 12.6.27.  PWM Generator x Select PCI Register Low 12.6.28.  PWM Generator x Select PCI Register High 12.6.29.  PWM Generator x Phase Register 12.6.30.  PWM Generator x Duty Cycle Register 12.6.31.  PWM Generator x Duty Cycle Adjustment Register 12.6.32.  PWM Generator x Period Register 12.6.33.  PWM Generator x Trigger A Register 12.6.34.  PWM Generator x Trigger B Register 12.6.35.  PWM Generator x Trigger C Register 12.6.36.  PWM Generator x Dead-Time Register Low 12.6.37.  PWM Generator x Dead-Time Register High 12.6.38.  PWM Generator x Capture Register 13.  High-Speed, 12-Bit Analog-to-Digital Converter 13.1.  ADC Features Overview 13.1.1.  Temperature Sensor 13.2.  Analog-to-Digital Converter Resources 13.2.1.  Differential-Mode 13.2.2.  Key Resources 13.3.  ADC Control Registers 13.3.1.  ADC Control Register 1 Low 13.3.2.  ADC Control Register 1 High 13.3.3.  ADC Control Register 2 Low 13.3.4.  ADC Control Register 2 High 13.3.5.  ADC Control Register 3 Low 13.3.6.  ADC Control Register 3 High 13.3.7.  ADC Input Mode Control Register 0 Low 13.3.8.  ADC Input Mode Control Register 0 High 13.3.9.  ADC Input Mode Control Register 1 Low 13.3.10.  ADC Interrupt Enable Register Low 13.3.11.  ADC Interrupt Enable Register High 13.3.12.  ADC Data Ready Status Register Low 13.3.13.  ADC Data Ready Status Register High 13.3.14.  ADC Digital Comparator x Channel Enable Register Low (x = 0, 1, 2, 3) 13.3.15.  ADC Digital Comparator x Channel Enable Register High (x = 0, 1, 2, 3) 13.3.16.  ADC Comparator x Threshold Low Register 13.3.17.  ADC Comparator x Threshold High Register 13.3.18.  Oversampling Filter x Output Register (x = 0, 1, 2, 3) 13.3.19.  ADC Digital Filter x Control Register (x = 0, 1, 2, 3) 13.3.20.  ADC Channel Trigger 0 Selection Register Low 13.3.21.  ADC Channel Trigger 0 Selection Register High 13.3.22.  ADC Channel Trigger 1 Selection Registers Low 13.3.23.  ADC Channel Trigger 1 Selection Register High 13.3.24.  ADC Channel Trigger 2 Selection Registers Low 13.3.25.  ADC Channel Trigger 2 Selection Register High 13.3.26.  ADC Channel Trigger 3 Selection Registers Low 13.3.27.  ADC Channel Trigger 3 Selection Register High 13.3.28.  ADC Channel Trigger 4 Selection Registers Low 13.3.29.  ADC Channel Trigger 4 Selection Register High 13.3.30.  ADC Channel Trigger 5 Selection Registers Low 13.3.31.  ADC Digital Comparator x Control Register (x = 0, 1, 2, 3) 13.3.32.  ADC Level-Sensitive Trigger Control Register Low 13.3.33.  ADC Level-Sensitive Trigger Control Register High 13.3.34.  ADC Early Interrupt Enable Register Low 13.3.35.  ADC Early Interrupt Enable Register High 13.3.36.  ADC Early Interrupt Status Register Low 13.3.37.  ADC Early Interrupt Status Register High 13.3.38.  ADC Control Register 5 Low 13.3.39.  ADC Control Register 5 High 13.3.40.  ADC Buffer x Register 14.  High-Speed Analog Comparator with Slope Compensation DAC 14.1.  Overview 14.2.  Features Overview 14.3.  DAC Control Registers 14.4.  DAC Control Registers 14.4.1.  DAC Control 1 Low Register 14.4.2.  DAC Control 2 Low Register 14.4.3.  DAC Control 2 High Register 14.4.4.  DACx Control Low Register 14.4.5.  DACx Control High Register 14.4.6.  DACx Data Low Register 14.4.7.  DACx Data High Register 14.4.8.  DACx Slope Control Low Register 14.4.9.  DACx Slope Control High Register 14.4.10.  DACx Slope Data Register 15.  Universal Asynchronous Receiver Transmitter (UART) 15.1.  Architectural Overview 15.2.  Character Frame 15.3.  Data Buffers 15.4.  Protocol Extensions 15.5.  UART Control/Status Registers 15.5.1.  UARTx Configuration Register 15.5.2.  UARTx Configuration Register High 15.5.3.  UARTx Status Register 15.5.4.  UARTx Status Register High 15.5.5.  UARTx Baud Rate Register 15.5.6.  UARTx Baud Rate Register High 15.5.7.  UARTx Receive Buffer Register 15.5.8.  UARTx Transmit Buffer Register 15.5.9.  UARTx Timing Parameter 1 Register 15.5.10.  UARTx Timing Parameter 2 Register 15.5.11.  UARTx Timing Parameter 3 Register 15.5.12.  UARTx Timing Parameter 3 Register High 15.5.13.  UARTx Transmit Checksum Register 15.5.14.  UARTx Receive Checksum Register 15.5.15.  UARTx Smart Card Configuration Register 15.5.16.  UARTx Smart Card Interrupt Register 15.5.17.  UARTx Interrupt Register 16.  Serial Peripheral Interface (SPI) 16.1.  SPI Control/Status Registers 16.1.1.  SPIx Control Register 1 Low 16.1.2.  SPIx Control Register 1 High 16.1.3.  SPIx Control Register 2 Low 16.1.4.  SPIx Status Register Low 16.1.5.  SPIx Status Register High 16.1.6.  SPIx Buffer Register Low 16.1.7.  SPIx Buffer Register High 16.1.8.  SPIx Baud Rate Generator Register Low 16.1.9.  SPIx Interrupt Mask Register Low 16.1.10.  SPIx Interrupt Mask Register High 16.1.11.  SPIx Underrun Data Register Low 16.1.12.  SPIx Underrun Data Register Low 17.  Inter-Integrated Circuit (I2C) 17.1.  Communicating as a Host in a Single Host Environment 17.2.  Setting Baud Rate When Operating as a Bus Main 17.3.  Secondary Address Masking 17.4.  SMBus Support 17.5.  I2C Control/Status Registers 17.5.1.  I2C1 Control Register Low 17.5.2.  I2C1 Control Register High 17.5.3.  I2C1 Status Register 17.5.4.  I2C1 Address Register 17.5.5.  I2C1 Client Mode Address Mask Register 17.5.6.  I2C1 Baud Rate Generator Register 17.5.7.  I2C1 Transmit Register 17.5.8.  I2C2 Receive Register 18.  Single-Edge Nibble Transmission (SENT) 18.1.  Transmit Mode 18.1.1.  Transmit Mode Configuration 18.1.1.1.  Initializing the SENTx Module 18.2.  Receive Mode 18.2.1.  Receive Mode Configuration 18.2.1.1.  Initializing the SENTx Module 18.3.  SENT Control/Status Registers 18.3.1.  SENT1 Control Register 1 18.3.2.  SENT1 Control Register 2 18.3.3.  SENT1 Control Register 3 18.3.4.  SENT1 Status Register 18.3.5.  SENT1 Sync Period Timer Register 18.3.6.  SENT1 Receive Data Register Low 18.3.7.  SENT1 Receive Data Register High 19.  Timer1 19.1.  Timer1 Control Registers 19.1.1.  Timer1 Control Register 19.1.2.  Timer1 Counter Register 19.1.3.  Period Register 1 20.  Capture/Compare/PWM/Timer Modules (SCCP) 20.1.  Time Base Generator 20.2.  General Purpose Timer 20.2.1.  Sync and Trigger Operation 20.3.  Output Compare Mode 20.4.  Input Capture Mode 20.5.  Auxiliary Output 20.6.  SCCP Control/Status Registers 20.6.1.  CCPx Control 1 Low Register 20.6.2.  CCPx Control 1 High Register 20.6.3.  Synchronization Sources 20.6.4.  CCPx Control 2 Low Register 20.6.5.  Auto-Shutdown and Gating Sources 20.6.6.  CCPx Control 2 High Register 20.6.7.  CCPx Control 3 High Register 20.6.8.  CCPx Status Register 20.6.9.  CCPx Status Register High 20.6.10.  CCPx Time Base Register Low 20.6.11.  CCPx Time Base High Register 20.6.12.  CCPx Period Low Register 20.6.13.  CCPx Period High Register 20.6.14.  CCPx Primary Compare Register Low (Timer/Compare Modes Only) 20.6.15.  CCPx Secondary Compare Register Low (Timer/Compare Modes Only) 20.6.16.  CCPx Capture Buffer Register Low (Capture Modes Only) 20.6.17.  CCPx Capture Buffer High Register (Capture Modes Only) 21.  Configurable Logic Cell (CLC) 21.1.  Control Registers 21.2.  CLC Control Registers 21.2.1.  CLCx Control Register Low 21.2.2.  CLCx Control Register High 21.2.3.  CLCx Input MUX Select Register 21.2.4.  CLCx Gate Logic Input Select Low Register 21.2.5.  CLCx Gate Logic Input Select High Register 22.  Peripheral Trigger Generator (PTG) 22.1.  Features 22.2.  PTG Registers 22.2.1.  PTG Control/Status Low Register 22.2.2.  PTG Control/Status Register 22.2.3.  PTG Broadcast Trigger Enable Low Register 22.2.4.  PTG Broadcast Trigger Enable Low Register 22.2.5.  PTG Hold Register 22.2.6.  PTG Timer0 Limit Register 22.2.7.  PTG Timer1 Limit Register 22.2.8.  PTG Step Delay Limit Register 22.2.9.  PTG Counter 0 Limit Register 22.2.10.  PTG Counter 1 Limit Register 22.2.11.  PTG Adjust Register 22.2.12.  PTG Literal 0 Register 22.2.13.  PTG Step Queue Pointer Register 22.2.14.  PTG Step Queue 0 Pointer Register 22.2.15.  PTG Step Queue 1 Pointer Register 22.2.16.  PTG Step Queue 2 Pointer Register 22.2.17.  PTG Step Queue 3 Pointer Register 22.2.18.  PTG Step Queue 4 Pointer Register 22.2.19.  PTG Step Queue 5 Pointer Register 22.2.20.  PTG Step Queue 6 Pointer Register 22.2.21.  PTG Step Queue 7 Pointer Register 22.2.22.  PTG Step Queue 8 Pointer Register 22.2.23.  PTG Step Queue 9 Pointer Register 22.2.24.  PTG Step Queue 10 Pointer Register 22.2.25.  PTG Step Queue 11 Pointer Register 22.2.26.  PTG Step Queue 12 Pointer Register 22.2.27.  PTG Step Queue 13 Pointer Register 22.2.28.  PTG Step Queue 14 Pointer Register 22.2.29.  PTG Step Queue 15 Pointer Register 22.3.  PTG Step Commands 23.  32-Bit Programmable Cyclic Redundancy Check (CRC) Generator 23.1.  CRC Control Registers 23.1.1.  CRC Control Register Low 23.1.2.  CRC Control Register High 23.1.3.  CRC XOR Polynomial Register, Low Byte 23.1.4.  CRC XOR Polynomial Register, High Byte 23.1.5.  CRC Data Register Low 23.1.6.  CRC Data Register High 23.1.7.  CRC Result Register Low 23.1.8.  CRC Result Register High 24.  Deadman Timer (DMT) 24.1.  Deadman Timer Control/Status Registers 24.1.1.  Deadman Timer Control Register 24.1.2.  Deadman Timer Preclear Register 24.1.3.  Deadman Timer Clear Register 24.1.4.  Deadman Timer Status Register 24.1.5.  Deadman Timer Count Register Low 24.1.6.  Deadman Timer Count Register High 24.1.7.  DMT Hold Register 24.1.8.  DMT Post-Configure Count Status Register Low 24.1.9.  DMT Post-Configure Count Status Register High 24.1.10.  DMT Post-Configure Interval Status Register Low 24.1.11.  DMT Post-Configure Interval Status Register High 25.  Power-Saving Features 25.1.  Clock Frequency and Clock Switching 25.2.  Instruction-Based Power-Saving Modes 25.2.1.  Sleep Mode 25.2.2.  Idle Mode 25.3.  Interrupts Coincident with Power Save Instructions 25.4.  Doze Mode 25.5.  Peripheral Module Disable 25.6.  Power-Saving Control Registers 25.6.1.  PMD Control Register 25.6.2.  Peripheral Module Disable 1 Control Register 25.6.3.  Peripheral Module Disable 2 Control Register 25.6.4.  Peripheral Module Disable 3 Control Register 25.6.5.  Peripheral Module Disable 4 Control Register 25.6.6.  Peripheral Module Disable 6 Control Register 25.6.7.  Peripheral Module Disable 7 Control Register 25.6.8.  Peripheral Module Disable 8 Control Register 25.7.  Power-Saving Resources 25.7.1.  Key Resources 26.  Dual Watchdog Timer (WDT) 26.1.  Watchdog Timer Control Register Low 26.2.  Watchdog Timer Control Register High 27.  Special Features 27.1.  Configuration Bits 27.2.  Configuration Registers 27.2.1.  FSEC Configuration Register 27.2.2.  FBSLIM Configuration Register 27.2.3.  FSIGN Configuration Register 27.2.4.  FOSCSEL Configuration Register 27.2.5.  FOSC Configuration Register 27.2.6.  FWDT Configuration Register 27.2.7.  FPOR Configuration Register 27.2.8.  FICD Configuration Register 27.2.9.  FDMTIVTL Configuration Register 27.2.10.  FDMTIVTH Configuration Register 27.2.11.  FDMTCNTL Configuration Register 27.2.12.  FDMTCNTH Configuration Register 27.2.13.  FDMT Configuration Register 27.2.14.  FDEVOPT Configuration Register 27.2.15.  FALTREG Configuration Register 27.3.  Device Calibration and Identification 27.3.1.  Device Revision Register 27.3.2.  Device ID Register 27.3.3.  Device IDs 27.4.  User OTP Memory 27.5.  On-Chip Voltage Regulator 27.5.1.  Voltage Regulator Control Register 27.6.  Brown-out Reset (BOR) 27.7.  JTAG Interface 27.8.  In-Circuit Serial Programming™ (ICSP™) 27.9.  In-Circuit Debugger 27.10.  Code Protection and CodeGuard™ Security 28.  Instruction Set Summary 29.  Development Support 30.  Electrical Characteristics 30.1.  DC Characteristics 30.2.  AC Characteristics and Timing Parameters 31.  Packaging Information 31.1.  Package Marking Information 31.2.  Package Details 32.  Revision History 33.  Product Identification System Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature