Package Characteristics For -40°C ≤T ≤85°C, unless otherwise specified. All typicals at T = 25°C. A A ParameterSymbol Min.Typ.Max.UnitsTest ConditionsFig.Notes Input-Output Momentary V 3750 V RH ≤ 50%, t = 1 min, 3, 9 ISO rms Withstand Voltage* T = 25°C A Resistance, Input-Output R 1012 Ω V = 500 V 3 I-O I-O Capacitance, Input-Output C 0.6 pF f = 1 MHz 3 I-O *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equipment level safety specification, or Avago Application Note 1074, “Optocoupler Input-Output Endurance Voltage.” Notes: 1. Bypassing the power supply line is required with a 0.1 µF ceramic 5. The t propagation delay is measured from the 50% point on the PHL disc capacitor adjacent to each optocoupler as illustrated in Figure leading edge of the input pulse to the 1.5 V point on the leading 19. The power supply bus for the optocoupler(s) should be separate edge of the output pulse. from the bus for any active loads, otherwise a larger value of bypass 6. CM is the maximum tolerable rate of rise of the common mode H capacitor (up to 0.5 µF) may be needed to suppress regenerative voltage to assure that the output will remain in a high logic state feedback via the power supply. (i.e., V > 2.0 V). OUT 2. Peaking circuits may produce transient input currents up to 100 7. CM is the maximum tolerable rate of fall of the common mode L mA, 500 ns maximum pulse width, provided average current does voltage to assure that the output will remain in a low logic state not exceed 5 mA. (i.e., V < 0.8 V). OUT 3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted 8. C is the peaking capacitance. Refer to test circuit in Figure 8. P together, and pins 5, 6, 7, and 8 shorted together. 9. In accordance with UL 1577, each optocoupler is momentary with- 4. The t propagation delay is measured from the 50% point on the stand proof tested by applying an insulation test voltage ≥4500 PLH trailing edge of the input pulse to the 1.5 V point on the trailing Vrms for 1 second (leakage detection current limit, I ≤ 5 µA). This I-O edge of the output pulse. test is performed before the 100% production test for partial dis- charge (Method b) shown in the IEC/EN/DIN EN 60747-5-5 Insula- tion Character istics Table, if applicable. Figure 2. Typical input diode forward charac-Figure 3. Typical output voltage vs. forwardFigure 4. Typical logic high output current vs.teristics.input current vs. temperature.temperature. 8