Datasheet DCL540C01A (Toshiba) - 4

DCL54xx01A
5.1. Pin Functions
PIN DCL540 DCL540 DCL541 DCL541 DCL542 I/O DESCRIPTION NAME C01A L01A A01A L01A L01A D01A H01A B01A H01A H01A VDD1 1 1 1 1 1 - Power Supply, side 1 GND1 2,8 2,8 2,8 2,8 2,8 - GND connection for VDD1 , side 1 VI1 3 3 3 3 3 I Input, Channel1 VI2 4 4 4 4 4 I Input, Channel2 VI3 5 5 5 5 12 I Input, Channel3 VI4 6 11 6 11 11 I Input, Channel4 NC 7,10 - 7 - - - Non connected Input disable 1. Input pins on side 1 are disabled DIS1 - 7 - - - I when DIS1 is high, and in enabled state when DIS1 is low or open. Input enable 1. Input pins on side 1 are enabled when EN1 - - - 7 7 I EN2 is high or open, and in high impedance state when EN2 is low. GND2 9,15 9,15 9,15 9,15 9,15 - GND connection for VDD2, side 2 Input disable 2. Input pins on side 2 are disabled when DIS DIS 2 - 10 - - - I 2 is high, and in enabled state when DIS2 is low or open. Input enable 2. Input pins on side 2 are enabled when EN EN 2 - - 10 10 10 I 2 is high or open, and in high impedance state when EN2 is low. Vo4 11 6 11 6 6 O Output, Channel4 Vo3 12 12 12 12 5 O Output, Channel3 Vo2 13 13 13 13 13 O Output, Channel2 Vo1 14 14 14 14 14 O Output, Channel1 VDD2 16 16 16 16 16 - Power Supply, side 2 4 2026-07-14 ©2026 Toshiba Electronic Devices & Storage Corporation Rev.1.4