Datasheet STM32G030x6, STM32G030x8 (STMicroelectronics) - 4
| Fabricante | STMicroelectronics |
| Descripción | Mainstream Value-Line Arm Cortex-M0+ MCU with 32 Kbytes of Flash memory, 8 Kbytes RAM, 64 MHz CPU, 2x USART, timers, ADC, comm |
| Páginas / Página | 100 / 4 — Contents. STM32G030x6/x8. Package information . 83. Ordering information … |
| Formato / tamaño de archivo | PDF / 2.1 Mb |
| Idioma del documento | Inglés |
Contents. STM32G030x6/x8. Package information . 83. Ordering information . 96. Important security notice . 97
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Contents STM32G030x6/x8
5.3.14 I/O port characteristics . 61 5.3.15 NRST input characteristics . 66 5.3.16 Extended interrupt and event controller input (EXTI) characteristics . 67 5.3.17 Analog switch booster . 67 5.3.18 Analog-to-digital converter characteristics . 68 5.3.19 Temperature sensor characteristics . 73 5.3.20 VBAT monitoring characteristics . 73 5.3.21 Timer characteristics . 73 5.3.22 Characteristics of communication interfaces . 74
6 Package information . 83
6.1 Device marking . 83 6.2 SO8N package information (O7) . 83 6.3 TSSOP20 package information (YA) . 86 6.4 LQFP32 package information (5V) . 88 6.5 LQFP48 package information (5B) . 92 6.6 Thermal characteristics . 95 6.6.1 Reference document . 95
7 Ordering information . 96 8 Important security notice . 97 9 Revision history . 98
4/100 DS12991 Rev 6 Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. STM32G030x6/x8 family device features and peripheral counts Figure 1. Block diagram 3 Functional overview 3.1 Arm® Cortex®-M0+ core with MPU 3.2 Memory protection unit 3.3 Embedded flash memory Table 3. Access status versus readout protection level and execution modes 3.4 Embedded SRAM 3.5 Boot modes 3.6 Cyclic redundancy check calculation unit (CRC) 3.7 Power supply management 3.7.1 Power supply schemes Figure 2. Power supply overview 3.7.2 Power supply supervisor 3.7.3 Voltage regulator 3.7.4 Low-power modes 3.7.5 Reset mode 3.7.6 VBAT operation 3.8 Interconnect of peripherals Table 4. Interconnect of peripherals 3.9 Clocks and startup 3.10 General-purpose inputs/outputs (GPIOs) 3.11 Direct memory access controller (DMA) 3.12 DMA request multiplexer (DMAMUX) 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) 3.13.2 Extended interrupt/event controller (EXTI) 3.14 Analog-to-digital converter (ADC) 3.14.1 Temperature sensor Table 5. Temperature sensor calibration values 3.14.2 Internal voltage reference (VREFINT) Table 6. Internal voltage reference calibration values 3.14.3 VBAT battery voltage monitoring 3.15 Timers and watchdogs Table 7. Timer feature comparison 3.15.1 Advanced-control timer (TIM1) 3.15.2 General-purpose timers (TIM3, 14, 16, 17) 3.15.3 Independent watchdog (IWDG) 3.15.4 System window watchdog (WWDG) 3.15.5 SysTick timer 3.16 Real-time clock (RTC), tamper (TAMP) and backup registers 3.17 Inter-integrated circuit interface (I2C) Table 8. I2C implementation 3.18 Universal synchronous/asynchronous receiver transmitter (USART) Table 9. USART implementation 3.19 Serial peripheral interface (SPI) Table 10. SPI/I2S implementation 3.20 Development support 3.20.1 Serial wire debug port (SW-DP) 4 Pinouts, pin description and alternate functions Figure 3. STM32G030Jx SO8N pinout Figure 4. STM32G030Fx TSSOP20 pinout Figure 5. STM32G030KxT LQFP32 pinout Figure 6. STM32G030CxT LQFP48 pinout Table 11. Terms and symbols used in Pin assignment and description table Table 12. Pin assignment and description Table 13. Port A alternate function mapping Table 14. Port B alternate function mapping Table 15. Port C alternate function mapping Table 16. Port D alternate function mapping Table 17. Port F alternate function mapping 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 7. Pin loading conditions Figure 8. Pin input voltage 5.1.6 Power supply scheme Figure 9. Power supply scheme 5.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme 5.2 Absolute maximum ratings Table 18. Voltage characteristics Table 19. Current characteristics Table 20. Thermal characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 21. General operating conditions 5.3.2 Operating conditions at power-up / power-down Table 22. Operating conditions at power-up / power-down 5.3.3 Embedded reset and power control block characteristics Table 23. Embedded reset and power control block characteristics 5.3.4 Embedded voltage reference Table 24. Embedded internal voltage reference Figure 11. VREFINT vs. temperature 5.3.5 Supply current characteristics Table 25. Current consumption in Run and Low-power run modes at different die temperatures Table 26. Current consumption in Sleep and Low-power sleep modes Table 27. Current consumption in Stop 0 mode Table 28. Current consumption in Stop 1 mode Table 29. Current consumption in Standby mode Table 30. Current consumption in VBAT mode Table 31. Current consumption of peripherals 5.3.6 Wakeup time from low-power modes and voltage scaling transition times Table 32. Low-power mode wakeup times Table 33. Regulator mode transition times 5.3.7 External clock source characteristics Table 34. High-speed external user clock characteristics Figure 12. High-speed external clock source AC timing diagram Table 35. Low-speed external user clock characteristics Figure 13. Low-speed external clock source AC timing diagram Table 36. HSE oscillator characteristics Figure 14. Typical application with an 8 MHz crystal Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 15. Typical application with a 32.768 kHz crystal 5.3.8 Internal clock source characteristics Table 38. HSI16 oscillator characteristics Table 39. LSI oscillator characteristics 5.3.9 PLL characteristics Table 40. PLL characteristics 5.3.10 Flash memory characteristics Table 41. Flash memory characteristics Table 42. Flash memory endurance and data retention 5.3.11 EMC characteristics Table 43. EMS characteristics Table 44. EMI characteristics 5.3.12 Electrical sensitivity characteristics Table 45. ESD absolute maximum ratings Table 46. Electrical sensitivity 5.3.13 I/O current injection characteristics Table 47. I/O current injection susceptibility 5.3.14 I/O port characteristics Table 48. I/O static characteristics Figure 16. I/O input characteristics Table 49. Input characteristics of FT_e I/Os Figure 17. Current injection into FT_e input with diode active Table 50. Output voltage characteristics Table 51. Non-FT_c I/O output timing characteristics Table 52. FT_c I/O output timing characteristics Figure 18. I/O AC characteristics definition 5.3.15 NRST input characteristics Table 53. NRST pin characteristics Figure 19. Recommended NRST pin protection 5.3.16 Extended interrupt and event controller input (EXTI) characteristics Table 54. EXTI input characteristics 5.3.17 Analog switch booster Table 55. Analog switch booster characteristics 5.3.18 Analog-to-digital converter characteristics Table 56. ADC characteristics Table 57. Maximum ADC RAIN . Table 58. ADC accuracy Figure 20. ADC accuracy characteristics Figure 21. ADC typical connection diagram 5.3.19 Temperature sensor characteristics Table 59. TS characteristics 5.3.20 VBAT monitoring characteristics Table 60. VBAT monitoring characteristics Table 61. VBAT charging characteristics 5.3.21 Timer characteristics Table 62. TIMx characteristics Table 63. IWDG min/max timeout period at 32 kHz LSI clock 5.3.22 Characteristics of communication interfaces Table 64. Minimum I2CCLK frequency Table 65. I2C analog filter characteristics Table 66. SPI characteristics Figure 22. SPI timing diagram - slave mode and CPHA = 0 Figure 23. SPI timing diagram - slave mode and CPHA = 1 Figure 24. SPI timing diagram - master mode Table 67. I2S characteristics Figure 25. I2S slave timing diagram (Philips protocol) Figure 26. I2S master timing diagram (Philips protocol) Table 68. USART characteristics in SPI mode Figure 27. USART timing diagram in SPI master mode Figure 28. USART timing diagram in SPI slave mode 6 Package information 6.1 Device marking 6.2 SO8N package information (O7) Figure 29. SO8N -Outline Table 69. SO8N -Mechanical data Figure 30. SO8N - Footprint example 6.3 TSSOP20 package information (YA) Figure 31. TSSOP20 – Outline Table 70. TSSOP20 – Mechanical data Figure 32. TSSOP20 – Footprint example 6.4 LQFP32 package information (5V) Figure 33. LQFP32 - Outline Table 71. LQFP32 - Mechanical data Figure 34. LQFP32 – Footprint example 6.5 LQFP48 package information (5B) Figure 35. LQFP48 - Outline(15) Table 72. LQFP48 - Mechanical data Figure 36. LQFP48 - Footprint example 6.6 Thermal characteristics Table 73. Package thermal characteristics 6.6.1 Reference document 7 Ordering information 8 Important security notice 9 Revision history Table 74. Document revision history (continued)
Contents STM32G030x6/x8
5.3.14 I/O port characteristics . 61 5.3.15 NRST input characteristics . 66 5.3.16 Extended interrupt and event controller input (EXTI) characteristics . 67 5.3.17 Analog switch booster . 67 5.3.18 Analog-to-digital converter characteristics . 68 5.3.19 Temperature sensor characteristics . 73 5.3.20 VBAT monitoring characteristics . 73 5.3.21 Timer characteristics . 73 5.3.22 Characteristics of communication interfaces . 74
6 Package information . 83
6.1 Device marking . 83 6.2 SO8N package information (O7) . 83 6.3 TSSOP20 package information (YA) . 86 6.4 LQFP32 package information (5V) . 88 6.5 LQFP48 package information (5B) . 92 6.6 Thermal characteristics . 95 6.6.1 Reference document . 95
7 Ordering information . 96 8 Important security notice . 97 9 Revision history . 98
4/100 DS12991 Rev 6 Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. STM32G030x6/x8 family device features and peripheral counts Figure 1. Block diagram 3 Functional overview 3.1 Arm® Cortex®-M0+ core with MPU 3.2 Memory protection unit 3.3 Embedded flash memory Table 3. Access status versus readout protection level and execution modes 3.4 Embedded SRAM 3.5 Boot modes 3.6 Cyclic redundancy check calculation unit (CRC) 3.7 Power supply management 3.7.1 Power supply schemes Figure 2. Power supply overview 3.7.2 Power supply supervisor 3.7.3 Voltage regulator 3.7.4 Low-power modes 3.7.5 Reset mode 3.7.6 VBAT operation 3.8 Interconnect of peripherals Table 4. Interconnect of peripherals 3.9 Clocks and startup 3.10 General-purpose inputs/outputs (GPIOs) 3.11 Direct memory access controller (DMA) 3.12 DMA request multiplexer (DMAMUX) 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) 3.13.2 Extended interrupt/event controller (EXTI) 3.14 Analog-to-digital converter (ADC) 3.14.1 Temperature sensor Table 5. Temperature sensor calibration values 3.14.2 Internal voltage reference (VREFINT) Table 6. Internal voltage reference calibration values 3.14.3 VBAT battery voltage monitoring 3.15 Timers and watchdogs Table 7. Timer feature comparison 3.15.1 Advanced-control timer (TIM1) 3.15.2 General-purpose timers (TIM3, 14, 16, 17) 3.15.3 Independent watchdog (IWDG) 3.15.4 System window watchdog (WWDG) 3.15.5 SysTick timer 3.16 Real-time clock (RTC), tamper (TAMP) and backup registers 3.17 Inter-integrated circuit interface (I2C) Table 8. I2C implementation 3.18 Universal synchronous/asynchronous receiver transmitter (USART) Table 9. USART implementation 3.19 Serial peripheral interface (SPI) Table 10. SPI/I2S implementation 3.20 Development support 3.20.1 Serial wire debug port (SW-DP) 4 Pinouts, pin description and alternate functions Figure 3. STM32G030Jx SO8N pinout Figure 4. STM32G030Fx TSSOP20 pinout Figure 5. STM32G030KxT LQFP32 pinout Figure 6. STM32G030CxT LQFP48 pinout Table 11. Terms and symbols used in Pin assignment and description table Table 12. Pin assignment and description Table 13. Port A alternate function mapping Table 14. Port B alternate function mapping Table 15. Port C alternate function mapping Table 16. Port D alternate function mapping Table 17. Port F alternate function mapping 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 7. Pin loading conditions Figure 8. Pin input voltage 5.1.6 Power supply scheme Figure 9. Power supply scheme 5.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme 5.2 Absolute maximum ratings Table 18. Voltage characteristics Table 19. Current characteristics Table 20. Thermal characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 21. General operating conditions 5.3.2 Operating conditions at power-up / power-down Table 22. Operating conditions at power-up / power-down 5.3.3 Embedded reset and power control block characteristics Table 23. Embedded reset and power control block characteristics 5.3.4 Embedded voltage reference Table 24. Embedded internal voltage reference Figure 11. VREFINT vs. temperature 5.3.5 Supply current characteristics Table 25. Current consumption in Run and Low-power run modes at different die temperatures Table 26. Current consumption in Sleep and Low-power sleep modes Table 27. Current consumption in Stop 0 mode Table 28. Current consumption in Stop 1 mode Table 29. Current consumption in Standby mode Table 30. Current consumption in VBAT mode Table 31. Current consumption of peripherals 5.3.6 Wakeup time from low-power modes and voltage scaling transition times Table 32. Low-power mode wakeup times Table 33. Regulator mode transition times 5.3.7 External clock source characteristics Table 34. High-speed external user clock characteristics Figure 12. High-speed external clock source AC timing diagram Table 35. Low-speed external user clock characteristics Figure 13. Low-speed external clock source AC timing diagram Table 36. HSE oscillator characteristics Figure 14. Typical application with an 8 MHz crystal Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 15. Typical application with a 32.768 kHz crystal 5.3.8 Internal clock source characteristics Table 38. HSI16 oscillator characteristics Table 39. LSI oscillator characteristics 5.3.9 PLL characteristics Table 40. PLL characteristics 5.3.10 Flash memory characteristics Table 41. Flash memory characteristics Table 42. Flash memory endurance and data retention 5.3.11 EMC characteristics Table 43. EMS characteristics Table 44. EMI characteristics 5.3.12 Electrical sensitivity characteristics Table 45. ESD absolute maximum ratings Table 46. Electrical sensitivity 5.3.13 I/O current injection characteristics Table 47. I/O current injection susceptibility 5.3.14 I/O port characteristics Table 48. I/O static characteristics Figure 16. I/O input characteristics Table 49. Input characteristics of FT_e I/Os Figure 17. Current injection into FT_e input with diode active Table 50. Output voltage characteristics Table 51. Non-FT_c I/O output timing characteristics Table 52. FT_c I/O output timing characteristics Figure 18. I/O AC characteristics definition 5.3.15 NRST input characteristics Table 53. NRST pin characteristics Figure 19. Recommended NRST pin protection 5.3.16 Extended interrupt and event controller input (EXTI) characteristics Table 54. EXTI input characteristics 5.3.17 Analog switch booster Table 55. Analog switch booster characteristics 5.3.18 Analog-to-digital converter characteristics Table 56. ADC characteristics Table 57. Maximum ADC RAIN . Table 58. ADC accuracy Figure 20. ADC accuracy characteristics Figure 21. ADC typical connection diagram 5.3.19 Temperature sensor characteristics Table 59. TS characteristics 5.3.20 VBAT monitoring characteristics Table 60. VBAT monitoring characteristics Table 61. VBAT charging characteristics 5.3.21 Timer characteristics Table 62. TIMx characteristics Table 63. IWDG min/max timeout period at 32 kHz LSI clock 5.3.22 Characteristics of communication interfaces Table 64. Minimum I2CCLK frequency Table 65. I2C analog filter characteristics Table 66. SPI characteristics Figure 22. SPI timing diagram - slave mode and CPHA = 0 Figure 23. SPI timing diagram - slave mode and CPHA = 1 Figure 24. SPI timing diagram - master mode Table 67. I2S characteristics Figure 25. I2S slave timing diagram (Philips protocol) Figure 26. I2S master timing diagram (Philips protocol) Table 68. USART characteristics in SPI mode Figure 27. USART timing diagram in SPI master mode Figure 28. USART timing diagram in SPI slave mode 6 Package information 6.1 Device marking 6.2 SO8N package information (O7) Figure 29. SO8N -Outline Table 69. SO8N -Mechanical data Figure 30. SO8N - Footprint example 6.3 TSSOP20 package information (YA) Figure 31. TSSOP20 – Outline Table 70. TSSOP20 – Mechanical data Figure 32. TSSOP20 – Footprint example 6.4 LQFP32 package information (5V) Figure 33. LQFP32 - Outline Table 71. LQFP32 - Mechanical data Figure 34. LQFP32 – Footprint example 6.5 LQFP48 package information (5B) Figure 35. LQFP48 - Outline(15) Table 72. LQFP48 - Mechanical data Figure 36. LQFP48 - Footprint example 6.6 Thermal characteristics Table 73. Package thermal characteristics 6.6.1 Reference document 7 Ordering information 8 Important security notice 9 Revision history Table 74. Document revision history (continued)