Datasheet CH32X033, CH32X035 (Nanjing Qinheng Microelectronics) - 9

CH32X035 Datasheet https://wch-ic.com
1.4.13 Timer and Watchdog
Advanced-control timer (TIM1, TIM2) The Advanced Control Timer is a 16-bit auto-loading up/down counter with a 16-bit programmable prescaler. In addition to the full general-purpose timer functionality, it can be viewed as a three-phase PWM generator assigned to 6 channels, with a complementary PWM output functionality with dead-time insertion, allowing the timer to be updated after a specified number of counter cycles for repeating counting cycle, braking function, etc. Many functions of advanced control timers are the same as general timers, and the internal structure is also the same. Therefore, advanced control timers can cooperate with other TIM timers through the timer link function to provide synchronization or event link functions. General-purpose timer (TIM3) The general-purpose timer is a 16-bit auto-loading recursive counter with a programmable 16-bit prescaler and 2 independent channels, each supporting input capture, output comparison, PWM generation and single pulse mode output. It can also work with advanced-control timers via the timer linking function to provide synchronous or event linking functionality. In debug mode, the counter can be frozen and any general-purpose timer can be used to generate PWM outputs. Independent watchdog The Independent Watchdog is a free-running 12-bit decrementing counter supporting 7 division factors. The clock source is provided by the division of the (HSI/1024) clock. IWDG works completely independently of the main program and can therefore be used to reset the entire system in case of problems or as a free timer to provide timeout management for applications. With the option byte it can be configured to be a software or hardware start watchdog. In debug mode, the counter can be frozen. Window watchdog Window watchdog is a 7-bit decrementing counter and can be set to run freely. It can be used to reset the entire system in the event of a problem. It is driven by the master clock and has an early warning interrupt function; in debug mode the counter can be frozen. SysTick timer QingKe microprocessor core comes with a 64-bit optional incremental or decremental counter for generating SYSTICK exceptions (exception number: 12), which can be used exclusively in real time operating systems to provide a "heartbeat" rhythm for the system, or as a standard 64-bit counter. Automatic reload function and programmable clock source.
1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART)
The chip provides 4 sets of universal synchronous/asynchronous transceivers. It supports full duplex asynchronous serial communication, synchronous unidirectional communication as well as half duplex single line communication, also LIN (Local Interconnect Network), ISO7816 compatible smart card protocol and IrDA SIR ENDEC transmission codec specification, as well as modem (CTS/RTS hardware flow control) operation, and also supports multi-processor communication. It uses a fractional baud rate generator system and supports continuous communication by DMA operation.
1.4.15 Serial Peripheral Interface (SPI)
The chip provides 1 serial peripheral SPI interface, support master or slave operation, dynamic switching. Support V2.3 7 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules