Datasheet 74HC4053, 74HCT4053 (NXP) - 10

FabricanteNXP
DescripciónTriple 2-channel analog multiplexer/demultiplexer
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NXP Semiconductors. 74HC4053; 74HCT4053. Triple 2-channel analog multiplexer/demultiplexer. Table 7

NXP Semiconductors 74HC4053; 74HCT4053 Triple 2-channel analog multiplexer/demultiplexer Table 7

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NXP Semiconductors 74HC4053; 74HCT4053 Triple 2-channel analog multiplexer/demultiplexer Table 7. Static characteristics for 74HC4053
…continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 6.0 V - - 8.0 A VCC = 10.0 V - - 16.0 A CI input capacitance - 3.5 - pF Csw switch capacitance independent pins nYn - 5 - pF common pins nZ - 8 - pF
Tamb =

40 C to +85 C
VIH HIGH-level input VCC = 2.0 V 1.5 - - V voltage VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V VIL LOW-level input VCC = 2.0 V - - 0.5 V voltage VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VCC = 9.0 V - - 2.7 V II input leakage current VEE = 0 V; VI = VCC or GND VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A IS(OFF) OFF-state leakage VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; current V   SW = VCC VEE; see Figure 11 per channel - - 1.0 A all channels - - 1.0 A I   S(ON) ON-state leakage VI = VIH or VIL; VSW = VCC VEE; - - 1.0 A current VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE VCC = 6.0 V - - 80.0 A VCC = 10.0 V - - 160.0 A
Tamb =

40 C to +125 C
VIH HIGH-level input VCC = 2.0 V 1.5 - - V voltage VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V VIL LOW-level input VCC = 2.0 V - - 0.5 V voltage VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VCC = 9.0 V - - 2.7 V 74HC_HCT4053 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 9 — 10 February 2016 10 of 31
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1 Additional dynamic characteristics 12. Package outline 13. Abbreviations 14. Revision history 15. Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks 16. Contact information 17. Contents