Datasheet LMC555 (Texas Instruments) - 9
| Fabricante | Texas Instruments |
| Descripción | CMOS Timer |
| Páginas / Página | 30 / 9 — LMC555. www.ti.com. Device Functional Modes (continued). Figure 4. … |
| Revisión | M |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
LMC555. www.ti.com. Device Functional Modes (continued). Figure 4. Monostable Waveforms. NOTE. Figure 5. Time Delay
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LMC555 www.ti.com
SNAS558M – FEBRUARY 2000 – REVISED JULY 2016
Device Functional Modes (continued)
VCC = 5 V Top Trace: Input 5 V/Div. TIME = 0.1 ms/Div. Middle Trace: Output 5 V/Div. RA = 9.1 kΩ Bottom Trace: Capacitor Voltage 2 V/Div. C = 0.01 µF
Figure 4. Monostable Waveforms
Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the desired tH. The minimum pulse width for the Trigger is 20 ns, and it is 400 ns for the Reset. During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal. The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not use, it is recommended that it be connected to V+ to avoid any possibility of false triggering. Figure 5 is a nomograph for easy determination of RC values for various time delays.
NOTE
In monstable operation, the trigger should be driven high before the end of timing cycle.
Figure 5. Time Delay
Copyright © 2000–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMC555 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-Power Dissipation 8.3.2 Various Packages and Compatibility 8.3.3 Operates in Both Astable and Monostable Mode 8.4 Device Functional Modes 8.4.1 Monostable Operation 8.4.2 Astable Operation 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curve 9.3 Frequency Divider 9.3.1 Design Requirements 9.3.2 Application Curve 9.4 Pulse Width Modulator 9.4.1 Design Requirements 9.4.2 Application Curve 9.5 Pulse Position Modulator 9.5.1 Design Requirements 9.5.2 Application Curve 9.6 50% Duty Cycle Oscillator 9.6.1 Design Requirements 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information
LMC555 www.ti.com
SNAS558M – FEBRUARY 2000 – REVISED JULY 2016
Device Functional Modes (continued)
VCC = 5 V Top Trace: Input 5 V/Div. TIME = 0.1 ms/Div. Middle Trace: Output 5 V/Div. RA = 9.1 kΩ Bottom Trace: Capacitor Voltage 2 V/Div. C = 0.01 µF
Figure 4. Monostable Waveforms
Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the desired tH. The minimum pulse width for the Trigger is 20 ns, and it is 400 ns for the Reset. During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal. The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not use, it is recommended that it be connected to V+ to avoid any possibility of false triggering. Figure 5 is a nomograph for easy determination of RC values for various time delays.
NOTE
In monstable operation, the trigger should be driven high before the end of timing cycle.
Figure 5. Time Delay
Copyright © 2000–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMC555 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-Power Dissipation 8.3.2 Various Packages and Compatibility 8.3.3 Operates in Both Astable and Monostable Mode 8.4 Device Functional Modes 8.4.1 Monostable Operation 8.4.2 Astable Operation 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curve 9.3 Frequency Divider 9.3.1 Design Requirements 9.3.2 Application Curve 9.4 Pulse Width Modulator 9.4.1 Design Requirements 9.4.2 Application Curve 9.5 Pulse Position Modulator 9.5.1 Design Requirements 9.5.2 Application Curve 9.6 50% Duty Cycle Oscillator 9.6.1 Design Requirements 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information