Datasheet SN74LVC1G74 (Texas Instruments) - 10

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SN74LVC1G74
SCES794E – OCTOBER 2009 – REVISED JANUARY 2015
www.ti.com 10 Application and Implementation NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connected directly to VCC to be inactive.
10.2 Typical Power Button Circuit
3 V 3 V 3 V NC VCC A GND Y CLK VCC SN74LVC1G17 D PRE Q CLR GND Q MCU SN74LVC1G74
Figure 4. Device Power Button Circuit 10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions: – For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table. – For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommend Output Conditions: – Load currents should not exceed 50 mA per output and 100 mA total for the part. – Series resistors on the output may be used if the user desires to slow the output edge signal or limit the 10 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 Document Outline 1 Features 2 Applications 3 Description 4 Simplified Schematic Table of Contents 5 Revision History 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Timing Requirements 7.7 Switching Characteristics 7.8 Operating Characteristics 7.9 Typical Characteristics 8 Parameter Measurement Information 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Power Button Circuit 10.2.1 Design Requirements 10.2.2 Detailed Design Procedure 10.2.3 Application Curves 11 Power Supply Recommendations 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Trademarks 13.2 Electrostatic Discharge Caution 13.3 Glossary 14 Mechanical, Packaging, and Orderable Information