Datasheet Texas Instruments ADS8363SRHBR — Ficha de datos

FabricanteTexas Instruments
SerieADS8363
Numero de parteADS8363SRHBR
Datasheet Texas Instruments ADS8363SRHBR

16 bits, 1-MSPS, 4x2 / 2x2 Muestreo simultáneo SAR ADC 32-VQFN -40 a 125

Hojas de datos

ADSxxx3 Dual, 1-MSPS, 16-, 14-, and 12-Bit, 4Г—2 or 2Г—2 Channel, Simultaneous Sampling Analog-to-Digital Converter datasheet
PDF, 1.4 Mb, Revisión: D, Archivo publicado: sept 2, 2017
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin32
Package TypeRHB
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Package QTY3000
CarrierLARGE T&R
Device MarkingADS8363
Width (mm)5
Length (mm)5
Thickness (mm).9
Pitch (mm).5
Max Height (mm)1
Mechanical DataDescargar

Paramétricos

# Input Channels4
Analog Voltage AVDD(Max)5.5 V
Analog Voltage AVDD(Min)2.7 V
ArchitectureSAR
Digital Supply(Max)5.5 V
Digital Supply(Min)2.3 V
INL(Max)3 +/-LSB
Input Range(Max)5.5 V
Input TypeDifferential,Pseudo-Differential
Integrated FeaturesN/A
InterfaceSPI
Multi-Channel ConfigurationMultiplexed,Simultaneous Sampling
Operating Temperature Range-40 to 125 C
Package GroupVQFN
Package Size: mm2:W x L32VQFN: 25 mm2: 5 x 5(VQFN) PKG
Power Consumption(Typ)47.2 mW
RatingCatalog
Reference ModeExt,Int
Resolution16 Bits
SINAD92 dB
SNR93 dB
Sample Rate (max)1MSPS SPS
Sample Rate(Max)1 MSPS
THD(Typ)-98 dB

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: ADS8363EVM
    ADS8363 Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Using the Sequencer and Pseudo-Differential Features of the ADS8363
    PDF, 161 Kb, Archivo publicado: mayo 21, 2014
  • Interfacing to the ADS8363 Pseudo-Differential Operating Mode
    PDF, 548 Kb, Archivo publicado: agosto 4, 2014
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Serie: ADS8363 (2)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)