Datasheet Texas Instruments SN74LVTH574DWR — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH574
Numero de parteSN74LVTH574DWR
Datasheet Texas Instruments SN74LVTH574DWR

Flip-Flops de tipo D con borde octal de 3,3 V V ABT con salidas de 3 estados 20-SOIC -40 a 85

Hojas de datos

SN54LVTH574, SN74LVTH574 datasheet
PDF, 1.4 Mb, Revisión: G, Archivo publicado: sept 15, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin20
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVTH574
Width (mm)7.5
Length (mm)12.8
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical DataDescargar

Paramétricos

3-State OutputYes
Bits8
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)5 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupSOIC
Package Size: mm2:W x L20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V
tpd @ Nom Voltage(Max)4.5 ns

Plan ecológico

RoHSObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop