Datasheet Texas Instruments SN74LVTH574PWE4 — Ficha de datos
Fabricante | Texas Instruments |
Serie | SN74LVTH574 |
Numero de parte | SN74LVTH574PWE4 |
![Datasheet Texas Instruments SN74LVTH574PWE4](http://www.ti.com/graphics/folders/partimages/SN74LVTH574.jpg)
Chanclas de tipo D de 3,3 V V con borde octal activadas por borde con salidas de 3 estados 20-TSSOP -40 a 85
Hojas de datos
SN54LVTH574, SN74LVTH574 datasheet
PDF, 1.4 Mb, Revisión: G, Archivo publicado: sept 15, 2003
Extracto del documento
Precios
Estado
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No |
Embalaje
Pin | 20 |
Package Type | PW |
Industry STD Term | TSSOP |
JEDEC Code | R-PDSO-G |
Package QTY | 70 |
Carrier | TUBE |
Device Marking | LXH574 |
Width (mm) | 4.4 |
Length (mm) | 6.5 |
Thickness (mm) | 1 |
Pitch (mm) | .65 |
Max Height (mm) | 1.2 |
Mechanical Data | Descargar |
Paramétricos
3-State Output | Yes |
Bits | 8 |
F @ Nom Voltage(Max) | 160 Mhz |
ICC @ Nom Voltage(Max) | 5 mA |
Operating Temperature Range | -40 to 85 C |
Output Drive (IOL/IOH)(Max) | 64/-32 mA |
Package Group | TSSOP |
Package Size: mm2:W x L | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) PKG |
Rating | Catalog |
Schmitt Trigger | No |
Technology Family | LVT |
VCC(Max) | 3.6 V |
VCC(Min) | 2.7 V |
Voltage(Nom) | 3.3 V |
tpd @ Nom Voltage(Max) | 4.5 ns |
Plan ecológico
RoHS | Obediente |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, Archivo publicado: feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Linea modelo
Serie: SN74LVTH574 (13)
Clasificación del fabricante
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop