Datasheet Texas Instruments TMS320C6670ACYPA — Ficha de datos

FabricanteTexas Instruments
SerieTMS320C6670
Numero de parteTMS320C6670ACYPA
Datasheet Texas Instruments TMS320C6670ACYPA

Sistema en chip multinúcleo fijo y de coma flotante 841-FCBGA -40 a 100

Hojas de datos

TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip datasheet
PDF, 2.4 Mb, Revisión: D, Archivo publicado: marzo 7, 2012
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante

Embalaje

Pin841841841
Package TypeCYPCYPCYP
Package QTY444444
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device MarkingTMS320C6670CYP@2010 TIA1GHZ
Width (mm)242424
Length (mm)242424
Thickness (mm)2.822.822.82
Mechanical DataDescargarDescargarDescargar

Paramétricos

ApplicationsCommunications and Telecom
DRAMDDR3
DSP4 C66x
DSP MHz1000,1200 Max.
EMAC10/100/1000
GFLOPS64,76.8
Hardware AcceleratorsVCP2,TCP3d,TCP3e,FFT Coprocessor
On-Chip L2 Cache4096 KB
Operating Temperature Range-40 to 100,0 to 85 C
Other On-Chip Memory2048 KB
PCI/PCIe2 PCIe Gen2
Package Size: mm2:W x LSee datasheet (FCBGA) PKG
RatingCatalog
Serial I/OAIF2,I2C,RapidIO,SPI,UART
Serial RapidIO1 (four lanes)
Total On-Chip Memory6528 KB

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Development Kits: TMDSEVM6670
    TMS320C6670 Evaluation Modules
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Development Kits: TMDSEVM6678
    TMS320C6678 Evaluation Modules
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Daughter Cards: TMDXEVMPCI
    AMC to PCIe Adapter Card
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Development Kits: HL5CABLE
    Hyperlink Cable
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • JTAG Emulators/ Analyzers: TMDSEMU200-U
    XDS200 USB Debug Probe
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
    XDS560v2 System Trace USB & Ethernet Debug Probe
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
    XDS560v2 System Trace USB Debug Probe
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • AIF1-to-AIF2 Antenna Interface Migration Guide for KeyStone Devices
    PDF, 640 Kb, Archivo publicado: nov 9, 2010
  • Connecting AIF to FFTC Guide for KeyStone Devices
    PDF, 441 Kb, Archivo publicado: nov 9, 2010
  • Tuning VCP2 and TCP2 Bit Error Rate Performance
    PDF, 293 Kb, Archivo publicado: feb 11, 2011
    In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
  • Keystone NDK FAQ
    PDF, 54 Kb, Archivo publicado: oct 3, 2016
    This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices.
  • TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
    PDF, 3.2 Mb, Archivo publicado: oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
  • TI Keystone DSP PCIe SerDes IBIS-AMI Models
    PDF, 4.8 Mb, Archivo publicado: oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
  • SerDes Implementation Guidelines for KeyStone I Devices
    PDF, 590 Kb, Archivo publicado: oct 31, 2012
    The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
  • Hardware Design Guide for KeyStone Devices (Rev. C)
    PDF, 1.7 Mb, Revisión: C, Archivo publicado: sept 15, 2013
  • TMS320C66x DSP Generation of Devices (Rev. A)
    PDF, 245 Kb, Revisión: A, Archivo publicado: abr 25, 2011
  • KeyStone I DDR3 Initialization (Rev. E)
    PDF, 114 Kb, Revisión: E, Archivo publicado: oct 28, 2016
    The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, Archivo publicado: abr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, Archivo publicado: dic 13, 2011
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, Archivo publicado: nov 9, 2010
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, Archivo publicado: nov 9, 2010
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revisión: B, Archivo publicado: jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, Revisión: B, Archivo publicado: agosto 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore

Linea modelo

Clasificación del fabricante

  • Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP