Datasheet Texas Instruments THS1030IDW — Ficha de datos

FabricanteTexas Instruments
SerieTHS1030
Numero de parteTHS1030IDW
Datasheet Texas Instruments THS1030IDW

10 bits, 30 MSPS ADC Single Ch., Pin Comp. w / TLC876, Indicador de fuera de rango, PowerDown 28-SOIC -40 a 85

Hojas de datos

3-V to 5.5-V 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter datasheet
PDF, 1.0 Mb, Revisión: E, Archivo publicado: oct 30, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaObsoleto (El fabricante ha interrumpido la producción del dispositivo)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin28
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Device MarkingTJ1030
Width (mm)7.5
Length (mm)17.9
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical DataDescargar

Reemplazos

ReplacementADS825E
Replacement CodeP

Paramétricos

# Input Channels1
Analog Input BW(MHz)150
Approx. Price (US$)6.94 | 100u
ArchitecturePipeline
DNL(Max)(+/-LSB)1
ENOB(Bits)7.8
INL(Max)(+/-LSB)2
Input BufferNo
Input Range2V (p-p)
InterfaceParallel CMOS
Operating Temperature Range(C)-40 to 85
0 to 70
Package GroupTSSOP
Package Size: mm2:W x L (PKG)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ)(mW)150
RatingCatalog
Reference ModeExt
Int
Resolution(Bits)10
SFDR(dB)53
SINAD(dB)48.6
SNR(dB)49.4
Sample Rate(Max)(MSPS)30

Plan ecológico

RoHSDesobediente
Pb gratisNo

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200EVM: Low Cost Portable Power Supply
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Linea modelo

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)