Datasheet Texas Instruments THS1030 — Ficha de datos

FabricanteTexas Instruments
SerieTHS1030
Datasheet Texas Instruments THS1030

Convertidor analógico a digital (ADC) de 10 bits y 30 MSPS

Hojas de datos

3-V to 5.5-V 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter datasheet
PDF, 1.0 Mb, Revisión: E, Archivo publicado: oct 30, 2003
Extracto del documento
3-V to 5.5-V 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter (Rev. E)
PDF, 1.1 Mb, Revisión: E, Archivo publicado: oct 30, 2003

Precios

Estado

THS1030CDWTHS1030CDWG4THS1030CDWRTHS1030CPWTHS1030CPWRTHS1030IDWTHS1030IPWTHS1030IPWRTHS1030IPWRG4
Estado del ciclo de vidaObsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNoNoNo

Embalaje

THS1030CDWTHS1030CDWG4THS1030CDWRTHS1030CPWTHS1030CPWRTHS1030IDWTHS1030IPWTHS1030IPWRTHS1030IPWRG4
N123456789
Pin282828282828282828
Package TypeDWDWDWPWPWDWPWPWPW
Industry STD TermSOICSOICSOICTSSOPTSSOPSOICTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Device MarkingTH1030TH1030TH1030TH1030TJ1030TJ1030TJ1030TJ1030
Width (mm)7.57.57.54.44.47.54.44.44.4
Length (mm)17.917.917.99.79.717.99.79.79.7
Thickness (mm)2.352.352.35112.35111
Pitch (mm)1.271.271.27.65.651.27.65.65.65
Max Height (mm)2.652.652.651.21.22.651.21.21.2
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar
Package QTY5020005020002000
CarrierTUBELARGE T&RTUBELARGE T&RLARGE T&R

Paramétricos

Parameters / ModelsTHS1030CDW
THS1030CDW
THS1030CDWG4
THS1030CDWG4
THS1030CDWR
THS1030CDWR
THS1030CPW
THS1030CPW
THS1030CPWR
THS1030CPWR
THS1030IDW
THS1030IDW
THS1030IPW
THS1030IPW
THS1030IPWR
THS1030IPWR
THS1030IPWRG4
THS1030IPWRG4
# Input Channels111111111
Analog Input BW, MHz150150150150
Analog Input BW(MHz)150150150150150
Approx. Price (US$)6.94 | 100u6.94 | 100u6.94 | 100u6.94 | 100u6.94 | 100u
ArchitecturePipelinePipelinePipelinePipelinePipelinePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB1111
DNL(Max)(+/-LSB)11111
DNL(Typ), +/-LSB0.30.30.30.3
ENOB, Bits9999
ENOB(Bits)7.87.87.87.87.8
INL(Max), +/-LSB2222
INL(Max)(+/-LSB)22222
INL(Typ), +/-LSB1111
Input BufferNoNoNoNoNoNoNoNo
Input Range2V (p-p)2V (p-p)2V (p-p)222V (p-p)222V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70
Operating Temperature Range(C)-40 to 85
0 to 70
-40 to 85
0 to 70
-40 to 85
0 to 70
-40 to 85
0 to 70
-40 to 85
0 to 70
Package GroupTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size(mm2=WxL)28TSSOP: 62 mm2: 6.4 x 9.7
Package Size: mm2:W x L, PKG28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Package Size: mm2:W x L (PKG)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ), mW150150150150
Power Consumption(Typ)(mW)150150150150150
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExt
Int
Ext
Int
Ext
Int
Ext,IntExt,IntExt
Int
Ext,IntExt,IntInt
Ext
Resolution, Bits10101010
Resolution(Bits)1010101010
SFDR, dB53535353
SFDR(dB)5353535353
SINAD, dB48.648.648.648.6
SINAD(dB)48.648.648.648.648.6
SNR, dB49.449.449.449.4
SNR(dB)49.449.449.449.449.4
Sample Rate (max)(SPS)30MSPS
Sample Rate(Max), MSPS30303030
Sample Rate(Max)(MSPS)30303030

Plan ecológico

THS1030CDWTHS1030CDWG4THS1030CDWRTHS1030CPWTHS1030CPWRTHS1030IDWTHS1030IPWTHS1030IPWRTHS1030IPWRG4
RoHSDesobedienteDesobedienteDesobedienteObedienteObedienteDesobedienteObedienteObedienteObediente
Pb gratisNoNoNoNo

Notas de aplicación

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of thes
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
    As system bandwidths have increased, an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not, however, particula

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)