Datasheet Texas Instruments CDC536DBG4 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CDC536 |
| Numero de parte | CDC536DBG4 |
Controlador de reloj PLL de 3.3V con opciones de frecuencia 1 / 2x, 1x y 2x 28-SSOP
Hojas de datos
CDC536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 322 Kb, Revisión: G, Archivo publicado: jul 8, 2004
Extracto del documento
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | Sí |
Embalaje
| Pin | 28 |
| Package Type | DB |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 50 |
| Carrier | TUBE |
| Device Marking | CDC536 |
| Width (mm) | 5.3 |
| Length (mm) | 10.2 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | .65 |
| Max Height (mm) | 2 |
| Mechanical Data | Descargar |
Paramétricos
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 200 ps |
| Number of Outputs | 6 |
| Operating Frequency Range(Max) | 100 MHz |
| Operating Frequency Range(Min) | 25 MHz |
| Package Group | SSOP |
| Package Size: mm2:W x L | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 500 ps |
| tsk(o) | 500 ps |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, Archivo publicado: abr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
Linea modelo
Serie: CDC536 (4)
- CDC536DB CDC536DBG4 CDC536DBR CDC536DBRG4
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers