Datasheet Texas Instruments CDC7005 — Ficha de datos

FabricanteTexas Instruments
SerieCDC7005
Datasheet Texas Instruments CDC7005

Sincronizador de reloj de alto rendimiento, bajo nivel de ruido y baja inclinación que sincroniza el reloj de referencia con VCXO

Hojas de datos

3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet
PDF, 1.1 Mb, Revisión: L, Archivo publicado: jun 4, 2009
Extracto del documento

Precios

Estado

CDC7005RGZCDC7005RGZRCDC7005RGZRG4CDC7005RGZTCDC7005RGZTG4CDC7005ZVACDC7005ZVARCDC7005ZVAT
Estado del ciclo de vidaVista previa (El dispositivo ha sido anunciado pero no está en producción. Las muestras pueden o no estar disponibles)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNo

Embalaje

CDC7005RGZCDC7005RGZRCDC7005RGZRG4CDC7005RGZTCDC7005RGZTG4CDC7005ZVACDC7005ZVARCDC7005ZVAT
N12345678
Pin4848484848646464
Package TypeRGZRGZRGZRGZRGZZVAZVAZVA
Industry STD TermVQFNVQFNVQFNVQFNVQFNBGABGABGA
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-NS-PBGA-NS-PBGA-NS-PBGA-N
Width (mm)77777888
Length (mm)77777888
Thickness (mm).9.9.9.9.9.96.96.96
Pitch (mm).5.5.5.5.5.8.8.8
Max Height (mm)111111.41.41.4
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar
Package QTY250025002502503481000250
CarrierLARGE T&RLARGE T&RSMALL T&RSMALL T&RJEDEC TRAY (10+1)LARGE T&RSMALL T&R
Device MarkingCDC7005CDC7005CDC7005CDC7005CK7005ZCK7005ZCK7005Z

Paramétricos

Parameters / ModelsCDC7005RGZ
CDC7005RGZ
CDC7005RGZR
CDC7005RGZR
CDC7005RGZRG4
CDC7005RGZRG4
CDC7005RGZT
CDC7005RGZT
CDC7005RGZTG4
CDC7005RGZTG4
CDC7005ZVA
CDC7005ZVA
CDC7005ZVAR
CDC7005ZVAR
CDC7005ZVAT
CDC7005ZVAT
Approx. Price (US$)10.00 | 1ku
Divider Ratio1 to 161 to 161 to 161 to 161 to 161 to 161 to 161 to 16
Input LevelLVCMOS (REF_CLK)
LVPECL (VCXO_CLK)
LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)
No. of Outputs5
Number of Inputs11111111
Number of Outputs5555555
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Output Frequency(Max), MHz800800800800800800800
Output Frequency(Max)(MHz)800
Output Frequency(Min), MHz10101010101010
Output Frequency(Min)(MHz)10
Output LevelLVPECLLVPECLLVPECLLVPECLLVPECLLVPECLLVPECLLVPECL
Package GroupVQFNVQFNVQFNVQFNVQFNBGABGABGA
Package Size: mm2:W x L, PKG48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)64BGA: 64 mm2: 8 x 8(BGA)64BGA: 64 mm2: 8 x 8(BGA)64BGA: 64 mm2: 8 x 8(BGA)
Package Size: mm2:W x L (PKG)48VQFN: 49 mm2: 7 x 7(VQFN)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Special FeaturesOPAMP for Active Loop Filter
Programmable Delay
OPAMP for Active Loop Filter,Programmable DelayOPAMP for Active Loop Filter,Programmable DelayOPAMP for Active Loop Filter,Programmable DelayOPAMP for Active Loop Filter,Programmable DelayOPAMP for Active Loop Filter,Programmable DelayOPAMP for Active Loop Filter,Programmable DelayOPAMP for Active Loop Filter,Programmable Delay
Supply Voltage(Max), V3.63.63.63.63.63.63.6
Supply Voltage(Max)(V)3.6
Supply Voltage(Min), V3333333
Supply Voltage(Min)(V)3

Plan ecológico

CDC7005RGZCDC7005RGZRCDC7005RGZRG4CDC7005RGZTCDC7005RGZTG4CDC7005ZVACDC7005ZVARCDC7005ZVAT
RoHSDesobedienteObedienteObedienteObedienteObedienteObedienteObedienteObediente
Pb gratisNo

Notas de aplicación

  • Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies
    PDF, 353 Kb, Archivo publicado: dic 17, 2004
    This application brief presents phase-noise data taken on Texas Instruments CDC7005 jitter cleaner and synchronizer PLL. The phase noise performance of CDC7005 depends on thephase noise of the reference clock, the voltage-controlled crystal oscillator (VCXO) clock,and the CDC7005 itself. This applications brief shows the phase noise performance of the CDC7005 clock synthesizer at the most popula
  • Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)
    PDF, 1.3 Mb, Revisión: A, Archivo publicado: jul 19, 2005
  • Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B)
    PDF, 85 Kb, Revisión: B, Archivo publicado: dic 15, 2009
  • General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)
    PDF, 207 Kb, Revisión: A, Archivo publicado: dic 16, 2003
  • Basics of the CDC7005 Hold Function
    PDF, 233 Kb, Archivo publicado: abr 13, 2006
    The CDC7005 is a high-performance clock synthesizer and jitter cleaner with implemented hold functionality. The hold functionality can be used for fail-safe operation if the reference clock is missing. This application report describes the basis, the advantages, and the limitations of the CDC7005 hold functionality. Additionally, a discrete realization of a simplified external hold function is sho
  • Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
    PDF, 627 Kb, Archivo publicado: jun 25, 2004
    Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the

Linea modelo

Clasificación del fabricante

  • Semiconductors> Clock and Timing> Clock Jitter Cleaners> Single-Loop PLL