Datasheet Texas Instruments DAC5672 — Ficha de datos

FabricanteTexas Instruments
SerieDAC5672
Datasheet Texas Instruments DAC5672

Convertidor digital a analógico (DAC) de doble canal, 14 bits, 275-MSPS

Hojas de datos

Dual 14 Bit 275 MSPS DAC datasheet
PDF, 1.7 Mb, Revisión: D, Archivo publicado: agosto 4, 2017
Extracto del documento
Dual 14 Bit 275 MSPS DAC (Rev. C)
PDF, 1.3 Mb, Revisión: C, Archivo publicado: nov 29, 2010

Precios

Estado

DAC5672IPFBDAC5672IPFBRDAC5672IPFBRG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

DAC5672IPFBDAC5672IPFBRDAC5672IPFBRG4
N123
Pin484848
Package TypePFBPFBPFB
Industry STD TermTQFPTQFPTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY25010001000
CarrierJEDEC TRAY (10+1)LARGE T&RLARGE T&R
Device MarkingDAC5672IDAC5672IDAC5672I
Width (mm)777
Length (mm)777
Thickness (mm)111
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical DataDescargarDescargarDescargar

Paramétricos

Parameters / ModelsDAC5672IPFB
DAC5672IPFB
DAC5672IPFBR
DAC5672IPFBR
DAC5672IPFBRG4
DAC5672IPFBRG4
Approx. Price (US$)13.40 | 1ku
ArchitectureCurrent SourceCurrent SourceCurrent Source
DAC Channels22
DAC: Channels2
IMD3(dBc)79
InterfaceParallel CMOSParallel CMOSParallel CMOS
Interpolation1x1x
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Package GroupTQFPTQFPTQFP
Package Size(mm2=WxL)48TQFP: 81 mm2: 9 x 9
Package Size: mm2:W x L, PKG48TQFP: 81 mm2: 9 x 9(TQFP)48TQFP: 81 mm2: 9 x 9(TQFP)
Power Consumption(Typ), mW330330
Power Consumption(Typ)(mW)330
RatingCatalogCatalogCatalog
Resolution, Bits1414
Resolution(Bits)14
SFDR, dB8484
SFDR(dB)84
SNR(dB)77
Sample / Update Rate, MSPS275275
Sample / Update Rate(MSPS)275
Settling Time(?s)0.02

Plan ecológico

DAC5672IPFBDAC5672IPFBRDAC5672IPFBRG4
RoHSObedienteObedienteObediente
Pb gratis

Notas de aplicación

  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, Archivo publicado: nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • High Speed Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, Revisión: A, Archivo publicado: oct 23, 2012
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, Archivo publicado: jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, Archivo publicado: nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the
  • High Speed, Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, Revisión: A, Archivo publicado: oct 23, 2012
    High Speed DAC (>10MSPS) High Speed, Digital-to-Analog Converters Basics
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, Archivo publicado: jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op amp differential to single-end
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
  • Superposition: The Hidden DAC Linearity Error
    PDF, 106 Kb, Archivo publicado: oct 2, 2000
    A digital-to analog converter (DAC) translates digital signals to analog signals. For example, a 12-bit DAC takes a 12-bit binary number, called an input code, and converts it into one of 4,096 analog

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)