Datasheet Texas Instruments DAC5672IPFB — Ficha de datos

FabricanteTexas Instruments
SerieDAC5672
Numero de parteDAC5672IPFB
Datasheet Texas Instruments DAC5672IPFB

Convertidor digital a analógico (DAC) de doble canal, 14 bits, 275-MSPS 48-TQFP -40 a 85

Hojas de datos

Dual 14 Bit 275 MSPS DAC datasheet
PDF, 1.7 Mb, Revisión: D, Archivo publicado: agosto 4, 2017
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante

Embalaje

Pin48
Package TypePFB
Industry STD TermTQFP
JEDEC CodeS-PQFP-G
Package QTY250
CarrierJEDEC TRAY (10+1)
Device MarkingDAC5672I
Width (mm)7
Length (mm)7
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

ArchitectureCurrent Source
DAC Channels2
InterfaceParallel CMOS
Interpolation1x
Operating Temperature Range-40 to 85 C
Package GroupTQFP
Package Size: mm2:W x L48TQFP: 81 mm2: 9 x 9(TQFP) PKG
Power Consumption(Typ)330 mW
RatingCatalog
Resolution14 Bits
SFDR84 dB
Sample / Update Rate275 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: DAC5672EVM
    DAC5672 Dual-Channel, 14-Bit, 275-MSPS Digital-to-Analog Converter Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: DAC5652EVM
    DAC5652 Dual-Channel, 10-Bit, 275-MSPS Digital-to-Analog Converter Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, Archivo publicado: nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • High Speed Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, Revisión: A, Archivo publicado: oct 23, 2012
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, Archivo publicado: jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Linea modelo

Serie: DAC5672 (3)

Clasificación del fabricante

  • Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)