Datasheet Texas Instruments SN65LVDS104DR — Ficha de datos
Fabricante | Texas Instruments |
Serie | SN65LVDS104 |
Numero de parte | SN65LVDS104DR |
Buffer de distribución de reloj LVDS 1: 4 16-SOIC -40 a 85
Hojas de datos
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revisión: G, Archivo publicado: dic 31, 2015
Extracto del documento
Precios
Estado
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No |
Embalaje
Pin | 16 |
Package Type | D |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 2500 |
Carrier | LARGE T&R |
Device Marking | LVDS104 |
Width (mm) | 3.91 |
Length (mm) | 9.9 |
Thickness (mm) | 1.58 |
Pitch (mm) | 1.27 |
Max Height (mm) | 1.75 |
Mechanical Data | Descargar |
Paramétricos
Input Frequency(Max) | 400 MHz |
Input Level | LVDS |
Number of Outputs | 4 |
Operating Temperature Range | -40 to 85 C |
Output Frequency(Max) | 400 MHz |
Output Level | LVDS |
Package Group | SOIC |
Package Size: mm2:W x L | 16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG |
Rating | Catalog |
VCC | 3.3 V |
VCC Out | 3.3 V |
Plan ecológico
RoHS | Obediente |
Notas de aplicación
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, Archivo publicado: feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Linea modelo
Serie: SN65LVDS104 (8)
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Differential