Datasheet Texas Instruments SN65LVDS104 — Ficha de datos
Fabricante | Texas Instruments |
Serie | SN65LVDS104 |
1: 4 búfer de distribución de reloj LVDS
Hojas de datos
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revisión: G, Archivo publicado: dic 31, 2015
Extracto del documento
Precios
Estado
SN65LVDS104D | SN65LVDS104DG4 | SN65LVDS104DR | SN65LVDS104DRG4 | SN65LVDS104PW | SN65LVDS104PWG4 | SN65LVDS104PWR | SN65LVDS104PWRG4 | |
---|---|---|---|---|---|---|---|---|
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | Sí | Sí | Sí | No | No | Sí | No | No |
Embalaje
SN65LVDS104D | SN65LVDS104DG4 | SN65LVDS104DR | SN65LVDS104DRG4 | SN65LVDS104PW | SN65LVDS104PWG4 | SN65LVDS104PWR | SN65LVDS104PWRG4 | |
---|---|---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
Pin | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
Package Type | D | D | D | D | PW | PW | PW | PW |
Industry STD Term | SOIC | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 40 | 40 | 2500 | 2500 | 90 | 90 | 2000 | 2000 |
Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R | TUBE | TUBE | LARGE T&R | LARGE T&R |
Device Marking | LVDS104 | LVDS104 | LVDS104 | LVDS104 | LVDS104 | LVDS104 | LVDS104 | LVDS104 |
Width (mm) | 3.91 | 3.91 | 3.91 | 3.91 | 4.4 | 4.4 | 4.4 | 4.4 |
Length (mm) | 9.9 | 9.9 | 9.9 | 9.9 | 5 | 5 | 5 | 5 |
Thickness (mm) | 1.58 | 1.58 | 1.58 | 1.58 | 1 | 1 | 1 | 1 |
Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 | .65 | .65 | .65 | .65 |
Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.75 | 1.2 | 1.2 | 1.2 | 1.2 |
Mechanical Data | Descargar | Descargar | Descargar | Descargar | Descargar | Descargar | Descargar | Descargar |
Paramétricos
Parameters / Models | SN65LVDS104D | SN65LVDS104DG4 | SN65LVDS104DR | SN65LVDS104DRG4 | SN65LVDS104PW | SN65LVDS104PWG4 | SN65LVDS104PWR | SN65LVDS104PWRG4 |
---|---|---|---|---|---|---|---|---|
Input Frequency(Max), MHz | 400 | 400 | 400 | 400 | 400 | 400 | 400 | 400 |
Input Level | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
Number of Outputs | 4 | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
Output Frequency(Max), MHz | 400 | 400 | 400 | 400 | 400 | 400 | 400 | 400 |
Output Level | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
Package Group | SOIC | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
Package Size: mm2:W x L, PKG | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) |
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
VCC, V | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 |
VCC Out, V | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 |
Plan ecológico
SN65LVDS104D | SN65LVDS104DG4 | SN65LVDS104DR | SN65LVDS104DRG4 | SN65LVDS104PW | SN65LVDS104PWG4 | SN65LVDS104PWR | SN65LVDS104PWRG4 | |
---|---|---|---|---|---|---|---|---|
RoHS | Obediente | Obediente | Obediente | Obediente | Obediente | Obediente | Obediente | Obediente |
Notas de aplicación
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, Archivo publicado: feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Linea modelo
Serie: SN65LVDS104 (8)
Clasificación del fabricante
- Semiconductors> Clock and Timing> Clock Buffers> Differential