Datasheet Texas Instruments SN65LVDS104 — Ficha de datos

FabricanteTexas Instruments
SerieSN65LVDS104
Datasheet Texas Instruments SN65LVDS104

1: 4 búfer de distribución de reloj LVDS

Hojas de datos

SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revisión: G, Archivo publicado: dic 31, 2015
Extracto del documento

Precios

Estado

SN65LVDS104DSN65LVDS104DG4SN65LVDS104DRSN65LVDS104DRG4SN65LVDS104PWSN65LVDS104PWG4SN65LVDS104PWRSN65LVDS104PWRG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

SN65LVDS104DSN65LVDS104DG4SN65LVDS104DRSN65LVDS104DRG4SN65LVDS104PWSN65LVDS104PWG4SN65LVDS104PWRSN65LVDS104PWRG4
N12345678
Pin1616161616161616
Package TypeDDDDPWPWPWPW
Industry STD TermSOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY404025002500909020002000
CarrierTUBETUBELARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingLVDS104LVDS104LVDS104LVDS104LVDS104LVDS104LVDS104LVDS104
Width (mm)3.913.913.913.914.44.44.44.4
Length (mm)9.99.99.99.95555
Thickness (mm)1.581.581.581.581111
Pitch (mm)1.271.271.271.27.65.65.65.65
Max Height (mm)1.751.751.751.751.21.21.21.2
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsSN65LVDS104D
SN65LVDS104D
SN65LVDS104DG4
SN65LVDS104DG4
SN65LVDS104DR
SN65LVDS104DR
SN65LVDS104DRG4
SN65LVDS104DRG4
SN65LVDS104PW
SN65LVDS104PW
SN65LVDS104PWG4
SN65LVDS104PWG4
SN65LVDS104PWR
SN65LVDS104PWR
SN65LVDS104PWRG4
SN65LVDS104PWRG4
Input Frequency(Max), MHz400400400400400400400400
Input LevelLVDSLVDSLVDSLVDSLVDSLVDSLVDSLVDS
Number of Outputs44444444
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Frequency(Max), MHz400400400400400400400400
Output LevelLVDSLVDSLVDSLVDSLVDSLVDSLVDSLVDS
Package GroupSOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
VCC, V3.33.33.33.33.33.33.33.3
VCC Out, V3.33.33.33.33.33.33.33.3

Plan ecológico

SN65LVDS104DSN65LVDS104DG4SN65LVDS104DRSN65LVDS104DRG4SN65LVDS104PWSN65LVDS104PWG4SN65LVDS104PWRSN65LVDS104PWRG4
RoHSObedienteObedienteObedienteObedienteObedienteObedienteObedienteObediente

Notas de aplicación

  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, Archivo publicado: feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Linea modelo

Clasificación del fabricante

  • Semiconductors> Clock and Timing> Clock Buffers> Differential