Datasheet AD5751 (Analog Devices) - 5

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Data Sheet AD5751 Parameter1 Min Typ Max Unit Test Conditions/Comments
Capacitive Load Stability TA = 25°C RLOAD = ∞ 1 nF RLOAD = 1 kΩ 1 nF RLOAD = ∞ 2 µF External compensation capacitor required; see Driving Large Capacitive Loads section DC Output Impedance 0.12 Ω Settling Time 0 V to 5 V Range, ¼ to ¾ Step 7 µs Specified with 2 kΩ || 220 pF, ±0.05% 0 V to 5 V Range, 40 mV Input Step 4.5 µs Specified with 2 kΩ || 220 pF, ±0.05% 0 V to 40 V Range, ¼ to ¾ Step 15.8 µs Specified with 5 kΩ || 220 pF, ±0.05% Slew Rate 2 V/µs Specified with 1 kΩ || 220 pF Output Noise 3.5 µV rms 0.1 Hz to 10 Hz bandwidth 45.5 µV rms 100 kHz bandwidth; specified with 2 kΩ || 220 pF Output Noise Spectral Density 165 nV/√Hz Measured at 10 kHz; specified with 2 kΩ || 220 pF AC PSRR 65 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage DC PSRR 10 µV/V CURRENT OUTPUT Output Current Ranges 0 24 mA 0 20 mA 3.92 20 mA Output Current Overranges2 0 24.5 mA See Detailed Description of Features section 0 20.4 mA See Detailed Description of Features section 3.92 20.4 mA See Detailed Description of Features section ACCURACY (INTERNAL RSET) Total Unadjusted Error (TUE) B Version3 −0.2 +0.2 % FSR −0.08 ±0.03 +0.08 % FSR TA = 25°C A Version3 −0.5 +0.5 % FSR −0.3 ±0.15 +0.3 % FSR TA = 25°C Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR Offset Error −16 +16 µa −10 +5 +10 µa TA = 25°C Offset Error TC4 ±3 ppm FSR/°C Dead Band on Output, RTI 8 +14 mV Referred to 4.096 V input range Gain Error −0.2 +0.2 % FSR −0.125 ±0.02 +0.125 % FSR TA = 25°C Gain TC4 ±10 ppm FSR/°C Full-Scale Error −0.2 +0.2 % FSR −0.125 ±0.02 +0.125 % FSR TA = 25°C Full-Scale TC4 ±4 ppm FSR/°C ACCURACY (EXTERNAL RSET) Total Unadjusted Error (TUE) B Version3 −0.1 +0.1 % FSR −0.08 ±0.03 +0.08 % FSR TA = 25°C A Version3 −0.3 +0.3 % FSR −0.1 ±0.02 +0.1 % FSR TA = 25°C Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR Offset Error −14 +14 µA −11 +5 +11 TA = 25°C Offset Error TC4 ±2 ppm FSR/°C Dead Band on Output, RTI 8 +14 mV Referred to 4.096 V input range Gain Error −0.08 +0.08 % FSR −0.07 ±0.02 +0.07 % FSR TA = 25°C Rev. D | Page 5 of 32 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Current Output Terminology Theory of Operation Software Mode Currrent Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5751 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide