Datasheet TDC-GPX2 (AustriaMicroSystems) - 11

TDC-GPX2 −
Converter Characteristics
Power Supply Characteristic
General Conditions: VDD33 = 3.3V; VDD18 = 1.8V; TA = 0°C to 80°C
Figure 10: Power Supply Characteristics Symbol Description Condition TL Min Typ Max Unit Supply Voltage
Delay from power-up of RVDD33 to TVDD18O, tVDD18O C CVDD18O, DVDD18O load = 100μF V 100 ms stable CMOS inputs and SPI Minimum total power read PTOT,MIN V 60 mW dissipation fREFCLK = 5MHz conversion rate 1MSPS LVDS inputs and outputs P f TOT,MAX Maximum total power REFCLK = 10MHz V 450 mW fSTOP1..4 = 50MHz fLCLK = 300MHz
Detailed Current Consumption
Core current into IDVDD18,REFCLK f REFCLK REFCLK = 5MHZ V 2 mA Current per stop IDVDD18,STOP V 0.5 mA channel Current with activated ICVDD18 V 14 mA TDC core Quartz oscillator ITVDD18,REFOSC f current if used REFOSC = 4MHZ III 2 mA IDVDD33,LVDS-IN Current per LVDS input III 2 6 mA ITVDD33,LVDS-IN buffer Current per LVDS IDVDD33,LVDS-OUT RTERM = 100Ω III 5 10 mA output buffer Quiescent current LVDS inputs tied to IDDQ II 60 100 μA mainly by IRVDD33 VDD33 LVDS, CMOS, Digital, ILKG Input leakage current II -5 1 μA REFOSCI
ams Datasheet Page 11
[v1-03] 2017-Dec-18 Document Feedback Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide