Datasheet AD9213 (Analog Devices) - 29

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Preliminary Technical Data AD9213
Figure 35 shows an example use case for coherent mode utilizing The following sequence describes the method for selecting the three NCO channels. In this example, NCO Channel 0 is actively active NCO channel using the profile select timer. downconverting bandwidth 0 (B0) when NCO Channel 1 and 1. Set NCO channel selection mode in Register 0x0632, NCO Channel 2 are in standby mode and tuned to Bandwidth 1 Bits[7:4] to 0xC to enable the profile select timer. (B1) and Bandwidth 2 (B2). 2. Configure the profile select timer by setting Register 0x65F The phase coherent NCO switching feature allows an infinite through Register 0x664. The profile select timer specifies number of frequency hops that are al phase coherent. The phase of the number of sample clock cycles between frequency the NCO is derived from the time stamp counter. The time stamp hops. counter is reset by the SYSREF± pin and/or the TRIG± pin. See 3. The NCO channel is incremented when the profile select time stamp counter section for details. timer expires. Switching the NCO FTW does not affect the phase. With this
NCO Synchronization
feature, only one FTW is required; however, the user may want to Each NCO contains a separate phase accumulator word (PAW). use al 16 channels to queue up the next hop. The initial reset value of each PAW is set to zero and increments After SYSREF± synchronization at start-up, all NCOs across every clock cycle. The instantaneous phase of the NCO is multiple chips are inherently synchronized. calculated using the PAW, FTW, MAW, MBW, and POW.
Setting Up the Multichannel NCO Feature
Two methods can be used to synchronize multiple PAWs within The first step to configure the multichannel NCO is to program the chip: the FTWs. The AD9213 memory map has a FTW index register • Using the SPI. Use the DDC soft reset bit in the DDC for the DDC. This index determines which NCO channel synchronization control register (Register 0x0600, Bit 4) to receives the FTW from the register map. The following reset all the PAWs in the chip. This reset is accomplished sequence describes the method for programming the FTWs. by setting the DDC soft reset bit high, and then setting this 1. Write the DDC profile (phase) update register (Register bit low. Note that this method can only be used to 0x633, Bit 7) to select the DDC profile (phase) update synchronize DDC channels within the same chip. mode. The update mode may be continuous or require • Using SYSREF: When the SYSREF± pin is enabled in the chip transfer. SYSREF control registers, and the DDC synchronization is 2. Write the FTW index register (Register 0x633, Bits[3:0]). enabled in the DDC synchronization control register 3. Write the FTW with the desired value. The FTW register (Register 0x600, Bits[1:0]), the next valid edge of SYSREF± addresses are 0x634, 0x635, 0x636, 0x637, 0x638, and or any subsequent edges of SYSREF± resets all the PAWs in 0x639. This value is applied to the NCO channel index the chip. Note that this method can be used to synchronize mentioned in Step 1. DDC channels within the same chip or DDC channels 4. Repeat Step 1 and Step 2 for other NCO channels. within separate chips. After setting the FTWs, the user must select an active NCO
NCO Multichip Synchronization
channel. This selection can be done through the SPI registers, In some applications, it is necessary to synchronize al the NCOs the external GPIOx pins, or a profile select timer. The following and local multiframe clocks (LMFCs) within multiple devices in sequence describes the method for selecting the active NCO a system. For applications requiring multiple NCO tuning channel using the SPI. frequencies in the system, a designer likely must generate a 1. Set the NCO channel selection mode in Register 0x0632, single SYSREF± pulse to al devices, simultaneously. Bits[7:4] to 0x0 to enable SPI selection. For many systems, generating or receiving a single-shot SYSREF± 2. Choose the active NCO channel in Register 0x632, Bits[3:0]. pulse on all devices is challenging because of the following The following sequence describes the method for selecting the factors: active NCO channel using GPIOx CMOS pins. • Enabling or disabling the SYSREF± pulse is often an 1. Set NCO channel selection mode in Register 0x0632, asynchronous event. Bits[7:4] to a value between 0x1 and 0xB to enable GPIOx • Not all clock generation chips support this feature. pin selection. For these reasons, the AD9213 contains a synchronization 2. Configure the GPIOx pins as NCO channel selection triggering mechanism that allows the following: inputs by writing to Register 0x1600. 3. • NCO switching is done by externally controlling the Multichip synchronization of all NCOs and LMFCs at GPIOx CMOS pins. system startup. • Multichip synchronization of all NCOs after applying new tuning frequencies during normal operation. Rev. PrG | Page 29 of 97 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9213-6G AD9213-10G EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Input Overvoltage Clamp VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Synthesis Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode and Sensor TMU ADC FAST DETECT FAST THRESHOLD DETECTION (FD) DIGITAL DOWNCONVERTER DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION Variable IF Mode ZIF Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode Example Calculation NCO FTW/POW/MAW/MAB Coherent Mode Example Calculation NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Profile Select Timer Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization during Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS M2_HB7 Filter Description M2_HB6 Filter Description M2_HB5 Filter Description M2_HB4 Filter Description M2_HB3 Filter Description M2_HB2 Filter Description M2_HB1 Filter Description M1_TB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop SETTING UP THE AD9213 DIGITAL INTERFACE JESD204B Transport Layer Settings Serial Line Rates K Settings DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION SAMPLED SYSREF MODE AVERAGED SYSREF MODE TEST MODES JESD204B TEST MODES SERIAL PORT INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER TABLES Open and Reserved Locations Default Values Logic Levels SPI Soft Reset REGISTER DETAILS: SYSTEM CONTROL SIGNALS (SPI_ONLY_REGMAP) REGISTER DETAILS: (USER_CTRL) REGISTER DETAILS: (AD9213_CUST_SPI_REGMAP) REGISTER DETAILS: (MAIN_REGMAP) REGISTER DETAILS: JTX_QBF REGISTER REGISTER DETAILS: DIG_DP_REGMAP REGISTER DETAILS: (AD9213_CUST_REG) REGISTER DETAILS: LCPLL_28NM REGISTER REGISTER DETAILS: JESD204B REGISTER MAP FOR FOUR CHANNELS (JTX_28NM_16CH) APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS