Datasheet ARG81800 (Allegro) - 4
| Fabricante | Allegro |
| Descripción | 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD |
| Páginas / Página | 42 / 4 — 40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow … |
| Formato / tamaño de archivo | PDF / 4.0 Mb |
| Idioma del documento | Inglés |
40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
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40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
VIN Bias VIN VREG LD 3.55 V UVLO 3.3 V Bias >3.15V EN REGOK BOOT BOOT REG LDO BG 0.8 V BIAS Bias OOV T 21.6 V 5.4 V UL VREG FA REGOK Current 2.5V Sense Amp BOOT Gcs EN t ENd DIS d FB OOV EN UVLO REGOK OCL Div 2 or 4 Start up or Hiccup LXGNDSC or Drop out toff
Protection & Fault
VINLXSC FSET PLL+ OSC Dither 500mΩ TSD FBUV SYNC FBOV IN HD CLK SW CLKOUT PWM
PWM/LP
T/2 COMP
Control
Slope
Logic
VREG Compensation Ramp LD 210 mΩ MODE PWM/ Offset T UL AUTO FA PGND MODE SLEEP 0.74 V GND FBUV PGOOD FBOV OCL 0.88 V Delay Overcurrent Hiccup, Dropout, Clamp Error Amp Stop-Start Recovery, FB Fault, Startup 0.8 V SS SS MODE LP Comparator SS Offset FB LP SLEEP Clamp 0.804 V MODE COMP
Functional Block Diagram
4 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
VIN Bias VIN VREG LD 3.55 V UVLO 3.3 V Bias >3.15V EN REGOK BOOT BOOT REG LDO BG 0.8 V BIAS Bias OOV T 21.6 V 5.4 V UL VREG FA REGOK Current 2.5V Sense Amp BOOT Gcs EN t ENd DIS d FB OOV EN UVLO REGOK OCL Div 2 or 4 Start up or Hiccup LXGNDSC or Drop out toff
Protection & Fault
VINLXSC FSET PLL+ OSC Dither 500mΩ TSD FBUV SYNC FBOV IN HD CLK SW CLKOUT PWM
PWM/LP
T/2 COMP
Control
Slope
Logic
VREG Compensation Ramp LD 210 mΩ MODE PWM/ Offset T UL AUTO FA PGND MODE SLEEP 0.74 V GND FBUV PGOOD FBOV OCL 0.88 V Delay Overcurrent Hiccup, Dropout, Clamp Error Amp Stop-Start Recovery, FB Fault, Startup 0.8 V SS SS MODE LP Comparator SS Offset FB LP SLEEP Clamp 0.804 V MODE COMP
Functional Block Diagram
4 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing