Datasheet PI6CB33601 (Diodes) - 2
| Fabricante | Diodes |
| Descripción | Very Low Power 6-Output PCIe Clock Buffer With On-Chip Termination |
| Páginas / Página | 20 / 2 — PI6CB33601. Pin Configuration. GND. Pin Description. Pin Number Pin Name. … |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
PI6CB33601. Pin Configuration. GND. Pin Description. Pin Number Pin Name. Type. Description
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A product Line of Diodes Incorporated
PI6CB33601 Pin Configuration
OE[7:0]# O O PD# V DD OE5# Q5- Q5+ OE4# Q4- Q4+ V DD V DD Q7 40 39 38 37 36 35 34 33 32 31 Q6 IN+ SADR_TRI 1 30 NC PLL IN- BW_SEL_TRI 2 29 OE3# Q5 NC 3 28 Q3- NC 4 27 Q3+ Q4 VDD_R 5 26 VDDO SCLK Q3 IN+ SDATA 6 25 VDDA
GND
SADR_TRI IN- 7 CTRL 24 OE2# BW_SEL_TRI LOGIC Q2 PD# GND_DIG 8 23 Q2- SCLK 9 22 Q2+ Q1 SDATA 10 21 OE1# 11 12 13 14 15 16 17 18 19 20 Q0 O O Q0+ Q0- Q1+ NC _DIG V DD OE0# VDD Q1- V DD V DD
Pin Description Pin Number Pin Name Type Description
1 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pull-down 2 BW_SEL_TRI Input Tri-level Latch to select low loop bandwidth, bypass PLL, and high loop band- width. This pin has both internal pull-up and pull-down 3 NC Internal connected for feedback loop. Do not connect this pin 4 NC Internal connected for feedback loop. Do not connect this pin 5 VDD_R Power Power supply for input differential buffers 6 IN+ Input Differential true clock input 7 IN- Input Differential complementary clock input 8 GND_DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 11 VDD_DIG Power Power supply for digital circuitry, nominal 3.3V 12, 17, 26, 32, 39 VDDO Power Power supply for differential outputs Active low input for enabling Q0 pair. This pin has an internal pull-down. 13 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 14 Q0+ Output HCSL Differential true clock output 15 Q0- Output HCSL Differential complementary clock output 16, 31 VDD Power Power supply, nominal 3.3V 18 Q1+ Output HCSL Differential true clock output PI6CB33601 www.diodes.com January 2020 Document Number DS41290 Rev 5-2 2 Diodes Incorporated
PI6CB33601 Pin Configuration
OE[7:0]# O O PD# V DD OE5# Q5- Q5+ OE4# Q4- Q4+ V DD V DD Q7 40 39 38 37 36 35 34 33 32 31 Q6 IN+ SADR_TRI 1 30 NC PLL IN- BW_SEL_TRI 2 29 OE3# Q5 NC 3 28 Q3- NC 4 27 Q3+ Q4 VDD_R 5 26 VDDO SCLK Q3 IN+ SDATA 6 25 VDDA
GND
SADR_TRI IN- 7 CTRL 24 OE2# BW_SEL_TRI LOGIC Q2 PD# GND_DIG 8 23 Q2- SCLK 9 22 Q2+ Q1 SDATA 10 21 OE1# 11 12 13 14 15 16 17 18 19 20 Q0 O O Q0+ Q0- Q1+ NC _DIG V DD OE0# VDD Q1- V DD V DD
Pin Description Pin Number Pin Name Type Description
1 SADR_TRI Input Tri-level Latch to select SMBus Address. This pin has an internal pull-down 2 BW_SEL_TRI Input Tri-level Latch to select low loop bandwidth, bypass PLL, and high loop band- width. This pin has both internal pull-up and pull-down 3 NC Internal connected for feedback loop. Do not connect this pin 4 NC Internal connected for feedback loop. Do not connect this pin 5 VDD_R Power Power supply for input differential buffers 6 IN+ Input Differential true clock input 7 IN- Input Differential complementary clock input 8 GND_DIG Power Ground for digital circuitry 9 SCLK Input CMOS SMBUS clock input, 3.3V tolerant 10 SDATA Input/ Output CMOS SMBUS Data line, 3.3V tolerant 11 VDD_DIG Power Power supply for digital circuitry, nominal 3.3V 12, 17, 26, 32, 39 VDDO Power Power supply for differential outputs Active low input for enabling Q0 pair. This pin has an internal pull-down. 13 OE0# Input CMOS 1 =disable outputs, 0 = enable outputs 14 Q0+ Output HCSL Differential true clock output 15 Q0- Output HCSL Differential complementary clock output 16, 31 VDD Power Power supply, nominal 3.3V 18 Q1+ Output HCSL Differential true clock output PI6CB33601 www.diodes.com January 2020 Document Number DS41290 Rev 5-2 2 Diodes Incorporated