Datasheet TLP5231 (Toshiba) - 4

TLP5231 7. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Note Rating Unit LED Input forward current IF 25 mA (controller Input forward current derating (Ta ≥ 95 ) ∆IF/∆Ta -0.84 mA/ side) Peak transient input forward IFPT (Note 1) 1 A current Peak transient input forward (Ta ≥ 95 ) ∆IFPT/∆Ta (Note 2) -34 mA/ current derating Input reverse voltage VR 5 V Positive input supply voltage VCC1 -0.5 to 7 V FAULT output current IFAULT 8 mA FAULT terminal voltage VFAULT -0.5 to VCC1 V Input power dissipation PD 150 mW Input power dissipation (Ta ≥ 95 ) ∆PD/∆Ta (Note 2) -5.0 mW/ derating Detector Peak high-level output current (Ta = -40 to 110 ) IOPH (Note 3) -2.5 A (gate Peak low-level output current (Ta = -40 to 110 ) IOPL (Note 3) +2.5 A driver side) Total output supply voltage (VCC2-VEE) (Note 4) -0.5 to 35 V Negative output supply voltage (VE-VEE) (Note 4) -0.5 to 17 V Positive output supply voltage (VCC2-VE) (Note 4) -0.5 to 30 V High side output voltage VOUTP(Peak) VE - 0.5 to VCC2 + 0.5 V Low side output voltage VOUTN(Peak) VEE - 0.5 to VE + 0.5 V DESAT voltage VDESAT VE - 0.5 to VCC2 + 0.5 V VGMOS voltage VGMOS VEE - 0.5 to VE + 0.5 V Output power dissipation PO 410 mW Output power dissipation (Ta ≥ 95 ) ∆PO/∆Ta (Note 2) -14.0 mW/ derating Common Operating temperature Topr -40 to 110 Storage temperature Tstg -55 to 125 Lead soldering temperature (10 s) Tsol (Note 5) 260 Isolation voltage (AC, 60 s, R.H. ≤ 60 %) BVS (Note 6) 5000 Vrms Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: Pulse width (PW) ≤ 1µs, 300pps Note 2: Mounting on the substrate made in accordance with JEDEC JESD51-7. Note 3: Exponential waveform. Pulse width ≤ 0.2 µs, f ≤ 15 kHz, VCC2 = 15 V Note 4: Positive and Negative power supply (VCC2/VEE) must be used in the gate drive circuit. Note 5: ≥ 2 mm below seating plane. Note 6: This device is considered as a two-terminal device: Pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together. ©2019-2020 4 2020-03-02 Toshiba Electronic Devices & Storage Corporation Rev.2.0