link to page 48 link to page 48 link to page 48 link to page 46 link to page 49 link to page 49 ADA4530-1Data SheetTable 13. Photodiode Interface DC Error Budget These low valued capacitors are designed for RF use and are Error Source25°C45°C60°C readily available. The 300 fF capacitor eliminates the frequency V peaking completely (blue curve) but it reduces the −3 dB OS 40 μV 40 μV + 10 μV 40 μV + 18 μV R bandwidth from 390 Hz to 50 Hz. SHUNT 5 GΩ 1.25 GΩ 442 MΩ Noise Gain 3 9 23 VSY = 10V V V OS Error RTO 120 μV 450 μV 1.3 mV CM = VSY/210TA = 25°C IB 20 fA 20 fA 20 fA ) Ω IB Error RTO 200 μV 200 μV 200 μV (G IN Total Error RTO 320 μV 650 μV 1.5 mV A G Total Error RTI 32 fA 65 fA 150 fA EANC The total RTI error over the entire temperature range is less D1E P than 150 fA, which is equal to 300 ppm of the 500 pA full-scale IM S range. The low input bias current of the ADA4530-1 is not a RAN significant contributor to the total error over temperature. The T interaction of the offset voltage with the shunt resistance of the CF = 0fF photodiode is the most significant error source. CF = 300fF0.10.11101001k10k100k 407 This circuit was constructed as described with a 10 GΩ feed- FREQUENCY (Hz) 13405- back resistor (Ohmite RX-1M1008JE). The dc error performance Figure 129. Transimpedance Gain vs. Frequency was measured over the 25°C to 60°C temperature range (see Figure 128). The error increases rapidly with temperature as the The stability improvement can be seen in the time domain as shunt resistance changes the noise gain exponentially. The total well. The circuits step response to a 10 pA photocurrent is RTI error ranges from +2 fA to −10 fA, considerably lower than shown in Figure 130. The uncompensated circuit (red curve) the worst case error budget, as expected. shows considerable (20%) overshoot. The compensated circuit (blue curve) is overdamped. 202VSY = 10V404VCM = VSY/2VSY = 10V00T20A = 25°C2IPD = 10pA) A–20–200p)()VV)NTµfAm (–20–2E–40–4R (R (ERRAG–40–4RROTCURROLDE–60–6OEOI EV–60–6RRRTRTUTE F–80–8P–80–8EUTRO –100–10UT–100–10INP–120–12CF = 0fF–120–12CF = 300fF010203040506070 401 –140–14 05- TEMPERATURE (°C)0510152025303540 -400 134 TIME (ms) 3405 Figure 128. DC Error vs. Temperature 1 Figure 130. 10 pA Step Response The ac performance of the circuit was also measured. The circuit was initially constructed without a physical feedback A noise budget is constructed based on the Noise Analysis capacitor as a baseline. The transimpedance gain vs. frequency section. The RTO noise budget is separated into noise sources is shown in Figure 129. The 30% frequency peaking seen in the integrated with a low bandwidth (see Table 14) and those frequency response (red curve) indicates that the feedback loop integrated with a high bandwidth (see Table 15). is marginally compensated with parasitic capacitance. The low frequency noise contributors include the feedback A physical capacitor was added to improve the loop compensa- resistance, the shunt resistance and the amplifier current noise. tion. This capacitor is a 300 fF C0G ceramic in a Size 0805, Each of these sources has a −3 dB bandwidth equal to the signal surface-mount package (AVX UQCFVA0R3BAT2A\500). C0G bandwidth (50 Hz); this is equivalent to a noise bandwidth of ceramic capacitors are good candidates for electrometer circuits 79 Hz. The most significant noise source is the photodiode because they have adequate insulation resistance and dielectric shunt resistance by a large margin. The second most significant absorption performance. source is the feedback resistor. The amplifier current noise is so low that it can be ignored. Rev. B | Page 48 of 52 Document Outline FEATURES APPLICATIONS PIN CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 5 V NOMINAL ELECTRICAL CHARACTERISTICS 10 V NOMINAL ELECTRICAL CHARACTERISTICS 15 V NOMINAL ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS MAIN AMPLIFIER, DC PERFORMANCE MAIN AMPLIFIER, AC PERFORMANCE GUARD AMPLIFIER THEORY OF OPERATION ESD STRUCTURE INPUT STAGE GAIN STAGE OUTPUT STAGE GUARD BUFFER APPLICATIONS INFORMATION INPUT PROTECTION SINGLE-SUPPLY AND RAIL-TO-RAIL OUTPUT CAPACITIVE LOAD STABILITY EMI REJECTION RATIO HIGH IMPEDANCE MEASUREMENTS INPUT BIAS CURRENT INPUT RESISTANCE INPUT OFFSET VOLTAGE INSULATION RESISTANCE GUARDING DIELECTRIC RELAXATION HUMIDITY EFFECTS CONTAMINATION CLEANING AND HANDLING SOLDER PASTE SELECTION CURRENT NOISE CONSIDERATIONS LAYOUT GUIDELINES PHYSICAL IMPLEMENTATION OF GUARDING TECHNIQUES GUARD RING GUARD PLANE VIA FENCE CABLES AND CONNECTORS ELECTROSTATIC INTERFERANCE PHOTODIODE INTERFACE DC ERROR ANALYSIS AC ERROR ANALYSIS NOISE ANALYSIS DESIGN RECOMMENDATIONS DESIGN EXAMPLE POWER SUPPLY RECOMMENDATIONS POWER SUPPLY CONSIDERATIONS LONG-TERM DRIFT TEMPERATURE HYSTERESIS OUTLINE DIMENSIONS ORDERING GUIDE