Datasheet KSZ8862-16M, KSZ8862-32M (Microchip) - 10

KSZ8862-16M/-32M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number
65 X1 I 25 MHz crystal or oscillator clock connection. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects 66 X2 O to a 3.3V tolerant oscillator and X2 is a no connect. Note: Clock requirement is ±50 ppm for either crystal or oscillator. Hardware reset pin (active-low). This reset input is required minimum of 67 RSTN IPU 10 ms low after stable supply voltage 3.3V. 68 A15 I Address 15 69 A14 I Address 14 70 A13 I Address 13 71 A12 I Address 12 72 A11 I Address 11 73 A10 I Address 10 74 A9 I Address 9 75 A8 I Address 8 76 A7 I Address 7 77 A6 I Address 6 78 DGND GND Digital IO ground 3.3V digital V 79 VDDIO P DDIO input power supply for IO with well decoupling capaci- tors. 80 A5 I Address 5 81 A4 I Address 4 82 A3 I Address 3 83 A2 I Address 2 84 A1 I Address 1 85 NC I No Connect 86 NC I No Connect Byte Enable 1 Not, Active-low for Data byte 1 enable (don’t care in 8-bit 87 BE1N I bus mode). Byte Enable 0 Not, Active-low for Data byte 0 enable (there is an internal 88 BE0N I inverter enabled and connected to the BE1N for 8-bit bus mode). 89 NC I No Connect 90 DGND GND Digital core ground 1.2V digital core V 91 VDDC P DD input power supply from VDDCO (pin 24) through external Ferrite bead and capacitor. 3.3V digital V 92 VDDIO P DDIO input power supply for IO with well decoupling capaci- tors. 93 NC I No Connect 94 NC I No Connect 95 NC I No Connect 96 NC I No Connect 97 NC I No Connect 98 NC I No Connect 99 NC I No Connect 100 NC I No Connect 101 NC I No Connect DS00003324A-page 10

 2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service