Datasheet AD74413R (Analog Devices) - 46

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AD74413R Data Sheet ADC_RDY Functionality
• After 24 µs in continuous mode. The ADC_RDY pin asserts low at the end of a sequence of • After writing to either the ADC_CONV_CTRL register. conversions for either single conversion or continuous See Figure 54 and Figure 55 for timing diagrams of the conversion mode. ADC_RDY pin in single and continuous conversion modes. The pin deasserts in any of the following scenarios: • A 1 is written to the ADC_DATA_RDY status bit in the LIVE_STATUS register.
ADC_RDY ADC PROCESSING IDLE ChA ChB ChD D3 IDLE ChA ChB ChD D3 IDLE ChA ChB ChD D3 IDLE CONVERT ON ENABLED ENABLE CHANNELS CONVERSION ENABLE ENABLE CLEAR ADC_RDY CONVERSION CONVERSION STATUS BIT
020
SPI INTERFACE CNV CLR CNV CNV
22282- Figure 54. ADC_RDY Functionality in Single Conversion Mode
ADC_RDY PIN NEW CONVERSION DATA AVAILABLE
021
ADC PROCESSING IDLE ChA ChB ChD D3 ChA ChB ChD D3 ChA ChB ChD D3 ChA ChB ChD D3
22282- Figure 55. ADC_RDY Functionality in Continuous Conversion Mode Rev. 0 | Page 46 of 70 Document Outline Features Applications General Description Companion Products Product Highlights Revision History Functional Block Diagram Specifications Voltage Output Current Output Voltage Input Current Input Externally Powered and Current Input Externally Powered with HART Current Input Loop Powered Resistance Measurement Digital Input Logic Digital Input Loop Powered ADC Specifications General Specifications Timing Characteristics SPI Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Digital Input Resistance Measurement Reference ADC Supplies Theory of Operation Robust Architecture Serial Interface DAC Architecture ADC Overview Reference Reference Noise Charge Pump Power-On State of the AD74413R Device Functions High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpreting ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data HART Compatibility Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Thermocouple Measurement Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Externally Powered with HART Compatibility Mode Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered with HART Compatibility Mode Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Threshold Setting Digital Input Current Sink Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter Digital Input Counter Digital Input, Loop Powered Mode Interpreting ADC Data Getting Started Using Channel Functions Switching Channel Functions ADC Functionality ADC Conversion Rates ADC_RDYb Functionality ADC Output Data Format ADC Noise Diagnostics DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control HART Compliant Slew Driving Inductive Loads Reset Function Thermal Alert and Thermal Reset Faults and Alerts Channel Faults Power Supply Monitors GPO_x Pins SPI Interface and Diagnostics SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback Board Design and Layout Considerations Applications Information Register Map NOP Register Function Setup Register per Channel ADC Configuration Register per Channel Digital Input Configuration Register per Channel GPO Parallel Data Register GPO Configuration Register per Channel Output Configuration Register per Channel DAC Code Register per Channel DAC Clear Code Register per Channel DAC Active Code Register per Channel Digital Input Threshold Register ADC Conversion Control Register Diagnostics Select Register Digital Output Level Register ADC Conversion Results Register per Channel Diagnostic Results Registers per Diagnostic Channel Alert Status Register Live Status Register Alert Mask Register Debounced DIN Count Register per Channel Readback Select Register Thermal Reset Enable Register Command Register Scratch or Spare Register Silicon Revision Register Outline Dimensions Ordering Guide