Datasheet ADRV9009 (Analog Devices) - 125

Data Sheet ADRV9009 L205 DNI L202 RX1 DNI 0805 FOOTPRINT C205 RX1_IN+ J201 C202 3 RX1_BAL+ DNI 1 DNI RX1_UNBAL 1 BAL_OUT1 T201 UNBAL_IN 4 R205 DNI BAL_OUT2 DNI R202 DNI NC_6 GND GND_DC_FEED_RFGND 2 3 4 5 6 5 2 L204 C204 L207 C207 L201 C201 L203 C203 RX1_DC DNI DNI L206 DNI DNI DNI DNI DNI DNI DNI R230 C230 C206 RX1_IN– AGND DNI DNI DNI RX1_BAL– R206 DNI AGND AGND OVERLAP PADS AGND L212 DNI L209 RX2 DNI 0805 FOOTPRINT C212 RX2_IN+ J202 C209 3 RX2_BAL+ DNI 1 DNI RX2_UNBAL 1 BAL_OUT1 T202 UNBAL_IN 4 R212 DNI BAL_OUT2 DNI R209 DNI NC_6 GND GND_DC_FEED_RFGND 2 3 4 5 6 5 2 L211 C211 L214 C214 L208 C208 L210 C210 RX2_DC DNI DNI L213 DNI DNI DNI DNI DNI DNI DNI R231 C231 C213 RX2_IN– AGND DNI DNI DNI RX2_BAL– R213 DNI
74
AGND AGND OVERLAP PADS
-4
AGND
499 16 Figure 464. Receiver 1 and Receiver 2 Generic Matching Network Topology
ORX1 T205 J203 TCM1-83X+ ORX1_UNBAL C250 R216 ORX1_BAL– R219 ORX1_IN– 1 3 5 0Ω 18pF 2 4 0Ω 2 3 4 5 C215 C217 C218 C221 DNI DNI DNI DNI NC AGND 6 1 R220 ORX1_IN+ AGND AGND C244 C245 ORX1_BAL+ 0Ω 10pF 27pF DNI AGND ORX2 T207 J204 C251 TCM1-83X+ R223 ORX2_UNBAL 1 3 5 ORX2_BAL– R226 ORX2_IN– 0Ω 18pF 2 4 0Ω 2 3 4 5 C222 C224 DNI DNI C228 C225 DNI DNI NC AGND 6 1 AGND AGND R227 ORX2_IN+ C246 C247 ORX2_BAL+ 0Ω 10pF 27pF DNI
5 47 9-
AGND
1649 Figure 465. Observation Receiver 1 and Observation Receiver 2 Generic Matching Network Topology Rev. B | Page 125 of 127 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Receiver Input Impedance Terminology Theory of Operation Transmitter Receiver Observation Receiver Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9009-W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide