Datasheet ADN8835 (Analog Devices) - 18

link to page 18 link to page 18 link to page 20
ADN8835 Data Sheet APPLICATIONS INFORMATION TEC DRIVER LINEAR POWER VIN STAGE PVINL – TEC CURRENT SENSE + LDR LDR + – TEMPERATURE ERROR PID COMPENSATION AMPLIFIER AMPLIFIER LINEAR PGNDL AMPLIFIER TEC AV = RFB/(RTH + RX) – RFB/R AV = Z2/Z1 + PGNDL CHOPPER 1 CHOPPER 2 – IN1P IN2P OUT1 OUT2 SFB CONTROL IN1N IN2N PWM POWER VIN STAGE PVINS PWM MODULATOR PWM SW MOSFET DRIVER OSCILLATOR PGNDS PGNDS T1 T2 VREF IN1P IN1N OU IN2P IN2N OU V V REF/2 TEMPSET R Z Z R 1 2 FB RX V V OUT1 OUT2 RTH
033 14174- Figure 33. Signal Flow Block Diagram
SIGNAL FLOW
the gain of the differential output section is fixed at 5. For details The ADN8835 integrates two auto-zero amplifiers, defined as on the output drivers, see the MOSFET Driver Amplifier section. the Chopper 1 amplifier and the Chopper 2 amplifier. Both of the
THERMISTOR SETUP
amplifiers can be used as standalone amplifiers; therefore, the The thermistor has a nonlinear relationship to temperature; near implementation of temperature control can vary. Figure 33 optimal linearity over a specified temperature range can be achieved shows the signal flow through the ADN8835, and a typical with the proper value of a compensation resistor, RX, placed in implementation of the temperature control loop using the series with the thermistor. Chopper 1 amplifier and the Chopper 2 amplifier. First, the resistance of the thermistor must be known, where In Figure 33, the Chopper 1 and Chopper 2 amplifiers are config- ured as the thermistor input amplifier and the PID compensation • RLOW = RTH at TLOW amplifier, respectively. The thermistor input amplifier amplifies • RMID = RTH at TMID the thermistor voltage, and then outputs to the PID compensa- • RHIGH = RTH at THIGH tion amplifier. The PID compensation amplifier then compensates TLOW and THIGH are the endpoints of the temperature range and a loop response over the frequency domain. TMID is the average. In some cases, with only the β constant The output from the compensation loop at OUT2 is fed to the linear available, calculate RTH using the following equation: MOSFET gate driver. The voltage at LDR is fed with OUT2 into   1 1  the PWM MOSFET gate driver. Including the internal transistors, R =  R exp β −  TH R      T R T  Rev. B | Page 18 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE