Datasheet AD524 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | Precision Instrumentation Amplifier |
| Páginas / Página | 25 / 10 — AD524. Data Sheet. –140. G = 1000. G = 100. –120. A) 12. G = 10. n ±. … |
| Revisión | G |
| Formato / tamaño de archivo | PDF / 590 Kb |
| Idioma del documento | Inglés |
AD524. Data Sheet. –140. G = 1000. G = 100. –120. A) 12. G = 10. n ±. –100. ( NT 10. G = 1. –80. CURRE. RR (. –60. BI UT. –40. INP. –20. 100. 10k. 100k. 10M
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AD524 Data Sheet 16 –140 G = 1000 G = 100 14 –120 A) 12 G = 10 n ± –100 ( NT 10 G = 1 B) –80 d 8 CURRE RR ( –60 AS CM 6 BI UT –40 4 INP –20 2
014 011 00500-
0
00500-
0 0 5 10 15 20 0 10 100 1k 10k 100k 1M 10M INPUT VOLTAGE (±V) FREQUENCY (Hz)
Figure 11. Input Bias Current vs. Input Voltage Figure 14. CMRR vs. Frequency, RTI, Zero to 1000 Source Imbalance
30 0 ) ) V -p G = 1, 10, 100 µ 1 ( E LU 20 SE (V p A 2 N L V A 3 ESPO FIN R ER OM 4 W 10 FR PO 5 V OS L L Δ U F BANDWIDTH LIMITED 6
012 015
G = 1000 G = 100 G = 10
00500-
0
00500-
0 1 2 3 4 5 6 7 8 1k 10k 100k 1M WARM-UP TIME (Minutes) FREQUENCY (Hz)
Figure 12. Offset Voltage, RTI, Turn-On Drift Figure 15. Large Signal Frequency Response
10 8 1000 ) s µ V) 100 6 E (V/ (V/ T IN A A 10 R G 4 EW SL 1 G = 1000 2
013 016 00500-
0
00500-
0 10 100 1k 10k 100k 1M 10M 1 10 100 1000 FREQUENCY (Hz) GAIN (V/V)
Figure 13. Gain vs. Frequency Figure 16. Slew Rate vs. Gain Rev. G | Page 10 of 25 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION INPUT PROTECTION INPUT OFFSET AND OUTPUT OFFSET GAIN INPUT BIAS CURRENTS COMMON-MODE REJECTION GROUNDING SENSE TERMINAL REFERENCE TERMINAL PROGRAMMABLE GAIN AUTO-ZERO CIRCUITS ERROR BUDGET ANALYSIS REFERENCES OUTLINE DIMENSIONS ORDERING GUIDE
014 011 00500-
0
00500-
0 0 5 10 15 20 0 10 100 1k 10k 100k 1M 10M INPUT VOLTAGE (±V) FREQUENCY (Hz)
Figure 11. Input Bias Current vs. Input Voltage Figure 14. CMRR vs. Frequency, RTI, Zero to 1000 Source Imbalance
30 0 ) ) V -p G = 1, 10, 100 µ 1 ( E LU 20 SE (V p A 2 N L V A 3 ESPO FIN R ER OM 4 W 10 FR PO 5 V OS L L Δ U F BANDWIDTH LIMITED 6
012 015
G = 1000 G = 100 G = 10
00500-
0
00500-
0 1 2 3 4 5 6 7 8 1k 10k 100k 1M WARM-UP TIME (Minutes) FREQUENCY (Hz)
Figure 12. Offset Voltage, RTI, Turn-On Drift Figure 15. Large Signal Frequency Response
10 8 1000 ) s µ V) 100 6 E (V/ (V/ T IN A A 10 R G 4 EW SL 1 G = 1000 2
013 016 00500-
0
00500-
0 10 100 1k 10k 100k 1M 10M 1 10 100 1000 FREQUENCY (Hz) GAIN (V/V)
Figure 13. Gain vs. Frequency Figure 16. Slew Rate vs. Gain Rev. G | Page 10 of 25 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION INPUT PROTECTION INPUT OFFSET AND OUTPUT OFFSET GAIN INPUT BIAS CURRENTS COMMON-MODE REJECTION GROUNDING SENSE TERMINAL REFERENCE TERMINAL PROGRAMMABLE GAIN AUTO-ZERO CIRCUITS ERROR BUDGET ANALYSIS REFERENCES OUTLINE DIMENSIONS ORDERING GUIDE