Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 14

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 PIN FUNCTION DESCRIPTIONS Table 11. Pin Descriptions State During/ Name Type After Reset Description
ADDR23–0 I/O/T (ipu) High-Z/
External Address.
The processor outputs addresses for external memory and periph- driven low erals on these pins. The ADDR pins can be multiplexed to support the external memory (boot) interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4 pins for parallel input data. DATA15–0 I/O/T (ipu) High-Z
External Data.
The data pins can be multiplexed to support the external memory interface data (I/O), and FLAGS7–0 (I/O). AMI_ACK I (ipu)
Memory Acknowledge.
External devices can deassert AMI_ACK (low) to add wait states to an external memory access. AMI_ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. MS0–1 O/T (ipu) High-Z
Memory Select Lines 0–1.
These lines are asserted (low) as chip selects for the corre- sponding banks of external memory. The MS1-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS1-0 lines are inactive; they are active however when a condi- tional memory access instruction is executed, when the condition evaluates as true. The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the hardware reference manual. AMI_RD O/T (ipu) High-Z
AMI Port Read Enable.
AMI_RD is asserted whenever the processor reads a word from external memory. AMI_WR O/T (ipu) High-Z
AMI Port Write Enable.
AMI_WR is asserted when the processor writes a word to external memory. FLAG0/IRQ0 I/O (ipu) FLAG[0]
FLAG0/Interrupt Request0.
INPUT FLAG1/IRQ1 I/O (ipu) FLAG[1]
FLAG1/Interrupt Request1.
INPUT FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2]
FLAG2/Interrupt Request2/Memory Select2.
INPUT FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3]
FLAG3/Timer Expired/Memory Select3.
INPUT The following symbols appear in the Type column of this table:
A
= asynchronous,
I
= input,
O
= output,
S
= synchronous,
A/D
= active drive,
O/D
= open drain, and
T
= three-state,
ipd
= internal pull-down resistor,
ipu
= internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The range of an ipd resistor can be between 31 kΩ–85 kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. Rev. H | Page 14 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide