Datasheet MP6925A (Monolithic Power Systems) - 9

MP6925A – FAST TURN-OFF, CCM/DCM DUAL LLC SYNCHRONOUS RECTIFIER Turn-Off Phase
Light-Load Mode Normal Mode When VDS rises to trigger the turn-off threshold, the gate voltage is pulled to zero after a very VDS tLL + tLL-H short turn-off delay (see Figure 3). VLL_DS
Turn-Off Blanking
VGS When VDS reaches the turn-off threshold and the gate driver is pulled to zero, turn-off blanking is triggered. This ensures that the gate ISD driver is off for a minimum time (tB_OFF) to prevent any erroneous triggers on VDS.

Secondary Side Current
Light-Load Latch-Off Function Figure 5: MP6925A Exiting Light-Load Mode
To improve efficiency, the MP6925A’s gate Light-load enter timing (t driver latches off to improve efficiency and LL) is configurable by connecting a resistor (R reduce driver loss under light-load conditions. LL) to LL. By monitoring the LL current (the LL voltage is kept at about The MP6925A compares the CH1 SR gate 2V internally), tLL can be calculated with (VG1) driver with the light-load enter pulse- Equation (1): width threshold (VLL-GS) every cycle to 2  determine the gate driver pulse width. If the .3 s t  R (k) (1) LL LL CH1 SR gate driver pulse width remains below 100k tLL every cycle for longer than the light-load If the LL pin resistor is disconnected, light-load enter delay (tLL-D), the MP6925A shuts down mode is disabled. In this case, it is both channel gates immediately and enters recommended to place a capacitor (typically light-load mode, which latches off the SR 22pF) on the LL pin to avoid noise.

MOSFET (see Figure 4). If the light-load mode of the MP6925A ends Normal Mode Light-Load Mode during the rectification cycle, the gate driver tLL-D signal does not appear until the next t < tLL t < tLL rectification cycle begins (see Figure 6). VGS VLL-GS
VDS
ISD
VGS Will not start
Secondary Side Current
gate driver until next cycle Figure 4: The MP6925A Enters Light-Load Mode Light-Load Mode Normal Mode
In light-load mode, the MP6925A monitors the body diode conduction time of CH1 by
Figure 6: Gate Driver Starts after Exiting Light-
comparing the drain-source voltage of the SR
Load Mode
MOSFET with the light-load exit switch-on
Anti-Bounce Logic
threshold (VLL_DS). If this time exceeds tLL + tLL-H, the IC exits light-load mode and initiates the The MP6925A has anti-bounce logic to protect gate driver in the next new switching cycle (see the two-channel driver from cross conduction. Figure 5 and Figure 6). Figure 7 shows the anti-bounce logic for the two-channel driver. When channel 1 or 2 are turned off, the corresponding channel gate MP6925A Rev. 1.0 www.MonolithicPower.com
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