Datasheet 6EDL7141 (Infineon) - 8

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6EDL7141
Datasheet
Pin Configuration 1.2 Pin Definitions and Functions
Table 2 describes the different characteristics and functionalities assigned to the different pin of 6EDL7141 device. I: Input, O: output, IO: Input and/or Output, D: Digital, A: Analog, AD: Analog and/or Digital, P: Power, G: Ground.
Table 2 Pin definition Pin # Pin Name IO Type Description
1 nSCS I D Chip Select for SPI. Active low 2 SCLK I D SPI clock signal 3 SDO O D SPI data output signal 4 SDI I D SPI data input signal When low indicates a fault has occurred; open drain; connect external 5 nFAULT O D pull-up to MCU power supply PWM input signal for channel A high side. Common PWM signal for 6 INHA I D PWM mode 1. Connect to DGND if not used PWM input signal for channel A low side. 7 INLA I D Input of Hall sensor A in 1PWM modes. Connect to DGND if not used 8 INHB I D PWM input signal for channel B high side. Connect to DGND if not used PWM input signal for channel B low side. 9 INLB I D Input of Hall sensor B in 1PWM modes. Connect to DGND if not used PWM input signal for channel C high side. 10 INHC I D DIR signal for 1PWM modes. Connect to DGND if not used PWM input signal for channel C low side. 11 INLC I D Input of Hall sensor C in 1PWM modes. Connect to DGND if not used Analog programming for the shunt amplifier gain. CS_GAIN/ 12 I A AZ Dual function as Auto-Zero: input to control external Auto-Zero function Analog programming of DVDD output voltage during start-up. Connect a pull down resistor to select DVDD voltage: VSENSE/ R<=3.3 kΩDVDD=3.3 V 13 I A/D nBRAKE R>= 10 kΩDVDD= 5.0 V After start-up, pin will be in nBRAKE mode: used for motor braking. Active low Supply for external MCU, Hall sensors, etc. Voltage is generated by 14 DVDD - P integrated linear voltage regulator and defined by VSENSE pin or SPI 15 PVDD - P Power supply of the device 16 PH - P Buck phase node voltage. Connect to output inductor 17 PGND - G Power ground used for buck converter, charge pumps and gate drivers 18 VDDB - P Buck output voltage. Connect capacitor between VDDB and PGND. 19 CP1L - P Bottom connection of the charge pump flying capacitor 1 20 CP1H - P Top connection of the charge pump flying capacitor 1 21 CP2L - P Bottom connection of the charge pump flying capacitor 2 22 CP2H - P Top connection of the charge pump flying capacitor 2
Datasheet
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<Revision 1.00> <2021-06-02>
Document Outline Product Feature Summary Potential Applications Product Description System Block Diagram Package Description 1 Pin Configuration 1.1 Pin Assignment 1.2 Pin Definitions and Functions 2 General Product Characteristics 2.1 Absolute Maximum Ratings 2.2 Recommended Operating Conditions 2.3 ESD Robustness 2.4 Thermal Resistance 2.5 Electrical Characteristics 2.6 Electrical Characteristic Graphs 3 Product Features 3.1 Functional Block Diagram 3.2 PWM Modes 3.2.1 PWM with 6 Independent Inputs – 6PWM 3.2.2 PWM with 3 Independent Inputs – 3PWM 3.2.3 PWM with 1 Input and Commutation Pattern – 1PWM 3.2.4 PWM with 1 Input and Commutation with Hall Sensor Inputs – 1PWM with Hall Sensors 3.2.5 PWM with 1 Input and Commutation with Hall Sensor Inputs and Alternating Recirculation – 1PWM with Hall Sensors and Alternating Recirculation 3.2.6 PWM Braking Modes 3.2.7 Dead Time Insertion 3.3 Integrated Three Phase Gate Driver 3.3.1 Gate Driver Architecture 3.3.2 Slew Rate Control 3.3.2.1 Slew Rate Control Parameters and Usage 3.3.3 Gate Driver Voltage Programmability 3.4 Charge Pump Configuration 3.4.1 Charge Pump Clock Frequency Selection 3.4.2 Charge Pump Clock Spread Spectrum Feature 3.4.3 Charge Pump Pre-Charge for VCCLS 3.4.4 Charge Pump Tuning 3.4.5 Gate Driver and Charge Pumps Protections 3.4.5.1 VCCLS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.2 VCCHS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.3 Floating Gate Strong Pull Down 3.5 Power Supply System 3.5.1 Synchronous Buck Converter Description 3.5.1.1 Buck Converter Output Voltage Dependency on PVCC_SETPT 3.5.1.2 Synchronous Buck Converter Protections 3.5.2 DVDD Linear Regulator 3.5.2.1 DVDD Linear Regulator OCP 3.6 Current Sense Amplifiers 3.6.1 RDSON Sensing Mode vs Leg Shunt Mode 3.6.2 Current Shunt Amplifier Timing Mode 3.6.3 Current Shunt Amplifier Blanking Time 3.6.4 Current Sense Amplifier Offset Generation: Internal or External (VREF pin) 3.6.5 Overcurrent Comparators and DAC for Current Sense Amplifiers 3.6.5.1 OCP Use Cases 3.6.5.2 OCP Fault Reporting 3.6.5.3 OCP Fault Latching 3.6.5.4 PWM Truncation 3.6.6 Current Sense Amplifier Gain Selection 3.6.7 Current Sense Amplifier DC Calibration 3.6.8 Auto-Zero Compensation of Current Sense Amplifier 3.6.8.1 Internal Auto-Zero 3.6.8.2 External Auto-Zero Synchronization via CS_GAIN/AZ Pin 3.6.8.3 External Auto-Zero Synchronization via CS_GAIN/AZ Pin with Enhanced Sensing 3.7 Hall Comparators 3.8 Watchdog Timers 3.8.1 Buck converter watchdog 3.8.2 General Purpose Watchdog 3.8.3 Locked-Rotor Protection Watchdog Timer 3.9 Multi-Function Pins 3.9.1 EN_DRV Pin 3.9.2 VSENSE/nBRAKE Pin 3.9.3 CS_GAIN/AZ Pin 3.10 ADC Module-Analog to Digital Converter 3.10.1 ADC Measurement Sequencing and On Demand Conversion 3.10.2 Die Temperature Sensor 4 Device Start-Up 4.1 Power Supply Start-Up 4.2 Gate Driver and CSAMP Start-up 5 Device Functional States 6 Protections and Faults Handling 7 Device Programming-OTP and SPI interface 7.1.1 OTP User Programming Procedure: Loading Custom Default Values 7.1.2 SPI Communication 7.1.2.1 SPI Communication Example 8 Register Map 8.1 Device Programmability 8.2 Register Map Faults Status Register Temperature Status Register Power Supply Status Register Functional Status Register OTP Status Register ADC Status Register Charge Pumps Status Register Device ID Register Faults Clear Register Power Supply Configuration Register ADC Configuration Register PWM Configuration Register Sensor Configuration Register Watchdog Configuration Register Watchdog Configuration Register 2 Gate Driver Current Control Register Gate Driver Pre-Charge Current Control Register TDRIVE Source Control Register TDRIVE Sink Control Register Dead Time Register Charge Pump Configuration Register Current Sense Amplifier Configuration Register Current Sense Amplifier Configuration Register 2 OTP Program Register 9 Application Description 9.1 Recommended External Components 9.2 PCB Layout Recommendations 9.3 Typical Applications 10 ESD Protection 11 Package Information Revision history