Databrief PIC18-Q71 (Microchip) - 9
| Fabricante | Microchip |
| Descripción | PIC18-Q71 Family Product Brief |
| Páginas / Página | 18 / 9 — PIC18-Q71. Pin Diagrams. Figure 2-5. 44-Pin TQFP. Note: . Figure … |
| Formato / tamaño de archivo | PDF / 249 Kb |
| Idioma del documento | Inglés |
PIC18-Q71. Pin Diagrams. Figure 2-5. 44-Pin TQFP. Note: . Figure 2-6. 48-Pin VQFN. Product Brief
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PIC18-Q71 Pin Diagrams Figure 2-5. 44-Pin TQFP
6 5 4 3 2 1 0 3 2 1 RC RC RC RD RD RD RD RC RC RC NC 44 43 42 41 40 39 38 37 36 35 34 RC7 1 33 NC RD4 2 32 RC0 RD5 3 31 RA6 RD6 4 30 RA7 RD7 5 29 VSS VSS 6 28 VDD VDD 7 27 RE2 RB0 8 26 RE1 RB1 9 25 RE0 RB2 10 24 RA5 RB3 11 23 RA4 12 13 14 15 16 17 18 19 20 21 22 4 5 6 7 3 0 1 2 3 NC NC RB RB RB RB RE RA RA RA RA / / / K R L AT L C D MC SP / SP C C PP I I V
Note:
It is recommended that the exposed bottom pad be connected to VSS.
Figure 2-6. 48-Pin VQFN
6 5 4 3 2 1 0 3 2 3 2 1 RC RC RC RD RD RD RD RC RC RF RF RF 48 47 46 45 44 43 42 41 40 39 38 37 RC7 1 36 RF0 RD4 2 35 RC1 RD5 3 34 RC0 RD6 4 33 RA6 RD7 5 32 RA7 VSS 31 6 VSS VDD 7 30 VDD RB0 8 29 RE2 28 RE1 RB1 9 RB2 10 27 RE0 26 RA5 RB3 11 25 RA4 12 RF4 13 14 15 16 17 18 19 20 21 22 23 24 5 6 7 4 5 6 7 3 0 1 2 3 RF RF RF RB RB RB RB RE RA RA RA RA / / / K R L AT L C D MC SP / SP C C PP I I V
Note:
It is recommended that the exposed bottom pad be connected to VSS. © 2021 Microchip Technology Inc.
Product Brief
DS40002289A-page 9 Document Outline Introduction PIC18-Q71 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
6 5 4 3 2 1 0 3 2 1 RC RC RC RD RD RD RD RC RC RC NC 44 43 42 41 40 39 38 37 36 35 34 RC7 1 33 NC RD4 2 32 RC0 RD5 3 31 RA6 RD6 4 30 RA7 RD7 5 29 VSS VSS 6 28 VDD VDD 7 27 RE2 RB0 8 26 RE1 RB1 9 25 RE0 RB2 10 24 RA5 RB3 11 23 RA4 12 13 14 15 16 17 18 19 20 21 22 4 5 6 7 3 0 1 2 3 NC NC RB RB RB RB RE RA RA RA RA / / / K R L AT L C D MC SP / SP C C PP I I V
Note:
It is recommended that the exposed bottom pad be connected to VSS.
Figure 2-6. 48-Pin VQFN
6 5 4 3 2 1 0 3 2 3 2 1 RC RC RC RD RD RD RD RC RC RF RF RF 48 47 46 45 44 43 42 41 40 39 38 37 RC7 1 36 RF0 RD4 2 35 RC1 RD5 3 34 RC0 RD6 4 33 RA6 RD7 5 32 RA7 VSS 31 6 VSS VDD 7 30 VDD RB0 8 29 RE2 28 RE1 RB1 9 RB2 10 27 RE0 26 RA5 RB3 11 25 RA4 12 RF4 13 14 15 16 17 18 19 20 21 22 23 24 5 6 7 4 5 6 7 3 0 1 2 3 RF RF RF RB RB RB RB RE RA RA RA RA / / / K R L AT L C D MC SP / SP C C PP I I V
Note:
It is recommended that the exposed bottom pad be connected to VSS. © 2021 Microchip Technology Inc.
Product Brief
DS40002289A-page 9 Document Outline Introduction PIC18-Q71 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables The Microchip Website Product Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service