Datasheet PIC16F627, PIC16F628 (Microchip) - 9

link to page 10 link to page 9 PIC16F62X 2.0 ARCHITECTURAL OVERVIEW The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless The high performance of the PIC16F62X family can be otherwise mentioned, arithmetic operations are two's attributed to a number of architectural features complement in nature. In two-operand instructions, commonly found in RISC microprocessors. To begin typically one operand is the working register with, the PIC16F62X uses a Harvard architecture, in (W register). The other operand is a file register or an which, program and data are accessed from separate immediate constant. In single operand instructions, the memories using separate buses. This improves operand is either the W register or a file register. bandwidth over traditional Von Neumann architecture The W register is an 8-bit working register used for ALU where program and data are fetched from the same operations. It is not an addressable register. memory. Separating program and data memory further allows instructions to be sized differently than 8-bit Depending on the instruction executed, the ALU may wide data word. Instruction opcodes are 14-bits wide affect the values of the Carry (C), Digit Carry (DC), and making it possible to have all single-word instructions. Zero (Z) bits in the STATUS register. The C and DC bits A 14-bit wide program memory access bus fetches a operate as a Borrow and Digit Borrow out bit, 14-bit instruction in a single cycle. A two-stage pipeline respectively, bit in subtraction. See the SUBLW and overlaps fetch and execution of instructions. SUBWF instructions for examples. Consequently, all instructions (35) execute in a single A simplified block diagram is shown in Figure 2-1, and cycle (200 ns @ 20 MHz) except for program a description of the device pins in Table 2-1. branches. Two types of data memory are provided on the The Table below lists program memory (FLASH, Data PIC16F62X devices. Non-volatile EEPROM data and EEPROM). memory is provided for long term storage of data such as calibration values, lookup table data, and any other TABLE 2-1: DEVICE DESCRIPTION data which may require periodic updating in the field. This data is not lost when power is removed. The other Memory data memory provided is regular RAM data memory. Device Regular RAM data memory is provided for temporary FLASH RAM EEPROM storage of data during normal operation. It is lost when Program Data Data power is removed. PIC16F627 1024 x 14 224 x 8 128 x 8 PIC16F628 2048 x 14 224 x 8 128 x 8 PIC16LF627 1024 x 14 224 x 8 128 x 8 PIC16LF628 2048 x 14 224 x 8 128 x 8 The PIC16F62X can directly or indirectly address its register files or data memory. All Special Function registers, including the program counter, are mapped in the data memory. The PIC16F62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any Addressing mode. This symmetrical nature, and lack of ‘special optimal situations’ make programming with the PIC16F62X simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16F62X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. 2003 Microchip Technology Inc. Preliminary DS40300C-page 7 Document Outline 1.0 PIC16F62X Device Varieties 2.0 Architectural Overview TABLE 2-1: Device Description FIGURE 2-1: BLOCK DIAGRAM FIGURE 2-2: CLOCK/INSTRUCTION CYCLE 3.0 Memory Organization FIGURE 3-1: Program Memory Map and Stack FIGURE 3-2: Data Memory Map of the PIC16F627 and PIC16F628 TABLE 3-1: Special Registers Summary Bank 0 TABLE 3-2: Special Function Registers Summary Bank 1 TABLE 3-3: Special Function Registers Summary Bank 2 TABLE 3-4: Special Function Registers Summary Bank 3 FIGURE 3-3: Loading Of PC In Different Situations FIGURE 3-4: Direct/Indirect Addressing PIC16F62X 4.0 General Description TABLE 4-1: PIC16F62X Family of Devices 5.0 I/O Ports FIGURE 5-1: Block Diagram of RA0/AN0:RA1/AN1 Pins FIGURE 5-2: Block Diagram of RA2/Vref Pin FIGURE 5-3: Block Diagram of the RA3/AN3 Pin FIGURE 5-4: Block Diagram of RA4/T0CKI Pin FIGURE 5-5: Block Diagram of the RA5/MCLR/Vpp Pin FIGURE 5-6: Block Diagram of RA6/OSC2/CLKOUT Pin FIGURE 5-7: Block Diagram of RA7/OSC1/CLKIN Pin TABLE 5-1: PORTA Functions TABLE 5-2: Summary of Registers Associated with PORTA(1) FIGURE 5-8: Block Diagram of RB0/INT Pin FIGURE 5-9: Block Diagram of RB1/RX/DT Pin FIGURE 5-10: Block Diagram of RB2/TX/CK Pin FIGURE 5-11: Block Diagram of RB3/CCP1 Pin FIGURE 5-12: Block Diagram of RB4/PGM Pin FIGURE 5-13: Block Diagram of RB5 Pin FIGURE 5-14: Block Diagram of RB6/T1OSO/T1CKI Pin FIGURE 5-15: Block Diagram of the RB7/T1OSI Pin TABLE 5-3: PORTB Functions TABLE 5-4: Summary of Registers Associated With PORTB(1) FIGURE 5-16: Successive I/O Operation 6.0 Timer0 Module FIGURE 6-1: Block Diagram of thE Timer0/WDT TABLE 6-1: Registers Associated with Timer0 7.0 Timer1 Module FIGURE 7-1: Timer1 Block Diagram TABLE 7-1: Capacitor Selection for the Timer1 Oscillator TABLE 7-2: Registers Associated with Timer1 as a Timer/Counter 8.0 Timer2 Module FIGURE 8-1: Timer2 Block Diagram TABLE 8-1: Registers Associated with Timer2 as a Timer/Counter 9.0 Comparator Module FIGURE 9-1: Comparator I/O Operating Modes FIGURE 9-2: Single Comparator FIGURE 9-3: Modified Comparator Output Block Diagram FIGURE 9-4: Analog Input Mode TABLE 9-1: Registers Associated with Comparator Module 10.0 Voltage Reference Module FIGURE 10-1: Voltage Reference Block Diagram FIGURE 10-2: Voltage Reference Output Buffer Example TABLE 10-1: Registers Associated with Voltage Reference 11.0 Capture/Compare/PWM (CCP) Module TABLE 11-1: CCP Mode - Timer Resource TABLE 11-2: Capture Mode Operation Block Diagram FIGURE 11-1: Compare Mode Operation Block Diagram TABLE 11-3: Registers Associated with Capture, compare, and Timer1 FIGURE 11-2: Simplified PWM Block Diagram FIGURE 11-3: PWM OUTPUT TABLE 11-4: Example PWM Frequencies and Resolutions at 20 MHz TABLE 11-5: Registers Associated with PWM and Timer2 12.0 Universal Synchronous/ Asynchronous Receiver/ Transmitter (USART) Module TABLE 12-1: BAUD rATE fORMULA TABLE 12-2: Registers Associated with Baud Rate Generator TABLE 12-3: Baud Rates for synchronous Mode TABLE 12-4: Baud Rates for Asynchronous Mode (BRGH = 0) TABLE 12-5: Baud Rates for Asynchronous Mode (BRGH = 1) FIGURE 12-1: RX Pin Sampling Scheme. BRGH = 0 FIGURE 12-2: RX Pin Sampling Scheme, BRGH = 1 FIGURE 12-3: RX Pin Sampling Scheme, BRGH = 1 FIGURE 12-4: RX Pin Sampling Scheme, BRGH = 0 OR BRGH = 1 FIGURE 12-5: USART Transmit Block Diagram FIGURE 12-6: Asynchronous Transmission FIGURE 12-7: Asynchronous Transmission (Back to Back) TABLE 12-6: Registers Associated with Asynchronous Transmission FIGURE 12-8: USART Receive Block Diagram FIGURE 12-9: Asynchronous Reception with Address Detect FIGURE 12-10: Asynchronous Reception with Address Byte First FIGURE 12-11: Asynchronous Reception with Address Byte First Followed by Valid Data Byte TABLE 12-7: Registers Associated with Asynchronous Reception TABLE 12-8: Registers Associated with Asynchronous Reception TABLE 12-9: Registers Associated with Synchronous Master Transmission FIGURE 12-12: Synchronous Transmission FIGURE 12-13: Synchronous Transmission (Through TXEN) TABLE 12-10: Registers Associated with Synchronous Master Reception FIGURE 12-14: Synchronous Reception (Master Mode, SREN) TABLE 12-11: Registers Associated with Synchronous Slave Transmission TABLE 12-12: Registers Associated with Synchronous Slave Reception 13.0 Data EEPROM Memory TABLE 13-1: Registers/Bits Associated with Data EEPROM 14.0 Special Features of the CPU FIGURE 14-1: Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration) TABLE 14-1: Capacitor Selection for Ceramic Resonators TABLE 14-2: Capacitor Selection for Crystal Oscillator FIGURE 14-2: External Parallel Resonant Crystal Oscillator Circuit FIGURE 14-3: External Series Resonant Crystal Oscillator Circuit FIGURE 14-4: External Clock Input Operation (EC, HS, XT or LP Osc Configuration) FIGURE 14-5: External Resistor TABLE 14-3: Resistance and Frequency Relationship FIGURE 14-6: Simplified Block Diagram of On-chip Reset Circuit FIGURE 14-7: Brown-out Situations TABLE 14-4: Timeout in Various Situations TABLE 14-5: Status/PCON Bits and Their Significance TABLE 14-6: Summary of Registers Associated with Brown-out TABLE 14-7: Initialization Condition for Special Registers TABLE 14-8: Initialization Condition for Registers FIGURE 14-8: Timeout Sequence on Power-up (MCLR not tied to Vdd): Case FIGURE 14-9: Timeout Sequence on Power-up (MCLR not tied to Vdd): Case 2 FIGURE 14-10: Timeout Sequence on Power-up (MCLR tied to Vdd) FIGURE 14-11: External Power-on Reset Circuit (For Slow Vdd Power-up) FIGURE 14-12: External Brown-out Protection Circuit 1 FIGURE 14-13: External Brown-out Protection Circuit 2 FIGURE 14-14: Interrupt Logic FIGURE 14-15: INT Pin Interrupt Timing TABLE 14-9: Summary of interrupt registers FIGURE 14-16: Watchdog Timer Block Diagram TABLE 14-10: Summary of Watchdog Timer Registers FIGURE 14-17: Wake-up from Sleep Through Interrupt FIGURE 14-18: Typical In-Circuit Serial Programming Connection 15.0 Instruction Set Summary TABLE 15-1: OPCODE Field Descriptions FIGURE 15-1: General Format for Instructions TABLE 15-2: PIC16F62X Instruction SeT 16.0 Development Support TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP 17.0 Electrical Specifications FIGURE 17-1: PIC16F62X VOLTAGE-FREQUENCY GRAPH, 0°C £ TA £ +70°C FIGURE 17-2: PIC16F62X VOLTAGE-FREQUENCY GRAPH, -40°C £ TA < 0°C, +70°C < TA £ 85°C FIGURE 17-3: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, 0°C £ TA £ +70°C FIGURE 17-4: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, -40°C £ TA < 0°C, +70°C < TA £ 85°C TABLE 17-1: Comparator Specifications TABLE 17-2: Voltage Reference Specifications FIGURE 17-5: Load Conditions TABLE 17-3: DC Characteristics: PIC16F62X, PIC16LF62X FIGURE 17-6: External Clock Timing TABLE 17-4: External Clock Timing Requirements FIGURE 17-7: CLKOUT and I/O Timing TABLE 17-5: CLKOUT and I/O Timing Requirements FIGURE 17-8: Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing FIGURE 17-9: Brown-out Detect Timing TABLE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements FIGURE 17-10: Timer0 and Timer1 External Clock Timings TABLE 17-7: Timer0 and Timer1 External Clock Requirements FIGURE 17-11: Capture/Compare/PWM Timings TABLE 17-8: Capture/Compare/PWM Requirements FIGURE 17-12: TIMER0 Clock Timing TABLE 17-9: TIMER0 Clock Requirements 18.0 DC and AC Characteristics Graphs and Tables FIGURE 18-1: Typical Idd vs Fosc over Vdd – HS Mode FIGURE 18-2: maximum Idd vs Fosc over Vdd (HS Mode) FIGURE 18-3: Typical Idd vs Fosc over Vdd (XT Mode) FIGURE 18-4: Maximum Idd vs Fosc over Vdd (XT Mode) FIGURE 18-5: Typical Idd vs Fosc over Vdd (LP Mode) FIGURE 18-6: Maximum Idd vs Fosc over Vdd (LP Mode) FIGURE 18-7: Typical Fosc vs Vdd (ER Mode) FIGURE 18-8: Typical Internal RC Fosc vs Vdd Temperature (-40 to 125°C) Internal 4MHz Oscillator FIGURE 18-9: Typical Internal RC Fosc vs Vdd OVER Temperature (-40 to 125°C) Internal 37kHz Osci... FIGURE 18-10: Ipd vs Vdd SLEEP mode, All Peripherals Disabled FIGURE 18-11: DLbod vs Voh Over Temperature (-40 to 125°C) FIGURE 18-12: DLtmr1osc vs Vdd Over Temp (0C to +70°C) Sleep Mode, Timer1 Oscillator, 32 khz XTAL FIGURE 18-13: DLwdt vs Vdd Sleep Mode, Watch Dog Timer Enabled FIGURE 18-14: DLcomp vs Vdd Sleep Mode, Comparators Enabled FIGURE 18-15: DLvref vs Vdd Sleep Mode, vref Enabled FIGURE 18-16: Minimum, Typical and Maximum WDT Period vs Vdd (-40°C to +125°C) FIGURE 18-17: Typical WDT Period vs Vdd (-40°C to +125°C) FIGURE 18-18: Voh vs Ioh Over Temp (C) Vdd = 5V FIGURE 18-19: Voh vs Ioh Over Temp (C) Vdd = 3V FIGURE 18-20: Vol vs Iol Over Temp (C) Vdd = 5V FIGURE 18-21: Vol vs Iol Over Temp (C) Vdd = 3V FIGURE 18-22: Vin vs Vdd TTL FIGURE 18-23: Vin vs Vdd ST Input FIGURE 18-24: Maximum Idd vs Vdd Over Temperature (-40 to +125°C) Internal 37kHz Oscillator FIGURE 18-25: Typical Idd vs Vdd Over Temperature (-40 TO +125˚C) Internal 37kHz Oscillator FIGURE 18-26: Maximum Idd vs Vdd Over Temperature (-40 to +125°C) Internal 4MHz Oscillator FIGURE 18-27: Typical Idd vs Vdd Over Temperature (-40 to +125°C) Internal 4MHz Oscillator 19.0 Packaging Information A B C D E G I M N O P Q R S T U V W X On-Line Support Systems Information and Upgrade Hot Line Reader Response Product Identification System Worldwide Sales