Datasheet RA2L2 (Renesas) - 2
| Fabricante | Renesas |
| Descripción | Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 128-KB code flash memory, 16-KB SRAM, USB 2.0 Full-Speed module (USBFS), USB Type-C® interface (USBCC), 12-bit A/D Converter, Security and Safety features. |
| Páginas / Página | 108 / 2 — Table 1.1. Arm core. Feature. Functional description. Table 1.2. Memory. … |
| Formato / tamaño de archivo | PDF / 2.0 Mb |
| Idioma del documento | Inglés |
Table 1.1. Arm core. Feature. Functional description. Table 1.2. Memory. Table 1.3. System (1 of 2)
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Versión de texto del documento
RA2L2 Datasheet 1. Overview 1. Overview The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability. The MCU in this series incorporates an energy-efficient Arm Cortex®-M23 32-bit core, that is particularly well suited for cost-sensitive and low-power applications, with the following features: ● Up to 128-KB code flash memory ● 16-KB SRAM ● USB 2.0 Full-Speed module (USBFS) ● USB Type-C interface (USBCC) ● 12-bit A/D Converter (ADC12) ● Security features 1.1 Function Outline
Table 1.1 Arm core Feature Functional description
Arm Cortex-M23 core ● Maximum operating frequency: up to 48 MHz ● Arm Cortex-M23 core: – Revision: r1p0-00rel0 – Armv8-M architecture profile – Single-cycle integer multiplier – 19-cycle integer divider ● Arm Memory Protection Unit (Arm MPU): – Armv8 Protected Memory System Architecture – 8 protect regions ● SysTick timer: – Driven by SYSTICCLK (LOCO) or ICLK
Table 1.2 Memory Feature Functional description
Code flash memory Maximum 128-KB of code flash memory. Data flash memory 4-KB of data flash memory. Option-setting memory The option-setting memory determines the state of the MCU after a reset. SRAM On-chip high-speed SRAM with parity bit.
Table 1.3 System (1 of 2) Feature Functional description
Operating modes Two operating modes: ● Single-chip mode ● SCI boot mode Resets The MCU provides 12 resets (RES pin reset, power-on reset, independent watchdog timer reset, watchdog timer reset, voltage monitor 0/1/2 resets, SRAM parity error reset, bus master/slave MPU error resets, CPU stack pointer error reset, software reset). Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level input to the VCC pin. LVD registers allow your application to configure detection of VCC changes at various voltage thresholds. R01DS0445EJ0110 Rev.1.10 Page 2 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice
Table 1.1 Arm core Feature Functional description
Arm Cortex-M23 core ● Maximum operating frequency: up to 48 MHz ● Arm Cortex-M23 core: – Revision: r1p0-00rel0 – Armv8-M architecture profile – Single-cycle integer multiplier – 19-cycle integer divider ● Arm Memory Protection Unit (Arm MPU): – Armv8 Protected Memory System Architecture – 8 protect regions ● SysTick timer: – Driven by SYSTICCLK (LOCO) or ICLK
Table 1.2 Memory Feature Functional description
Code flash memory Maximum 128-KB of code flash memory. Data flash memory 4-KB of data flash memory. Option-setting memory The option-setting memory determines the state of the MCU after a reset. SRAM On-chip high-speed SRAM with parity bit.
Table 1.3 System (1 of 2) Feature Functional description
Operating modes Two operating modes: ● Single-chip mode ● SCI boot mode Resets The MCU provides 12 resets (RES pin reset, power-on reset, independent watchdog timer reset, watchdog timer reset, voltage monitor 0/1/2 resets, SRAM parity error reset, bus master/slave MPU error resets, CPU stack pointer error reset, software reset). Low Voltage Detection (LVD) The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level input to the VCC pin. LVD registers allow your application to configure detection of VCC changes at various voltage thresholds. R01DS0445EJ0110 Rev.1.10 Page 2 of 108 Mar 12, 2025 Document Outline Features 1. Overview 1.1 Function Outline 1.2 Block Diagram 1.3 Part Numbering 1.4 Function Comparison 1.5 Pin Functions 1.6 Pin Assignments 1.7 Pin Lists 2. Electrical Characteristics 2.1 Absolute Maximum Ratings 2.2 DC Characteristics 2.2.1 Tj/Ta Definition 2.2.2 I/O VIH, VIL 2.2.3 I/O IOH, IOL 2.2.4 I/O VOH, VOL, and Other Characteristics 2.2.5 Operating and Standby Current 2.2.6 VCC Rise and Fall Gradient and Ripple Frequency 2.2.7 Thermal Characteristics 2.3 AC Characteristics 2.3.1 Frequency 2.3.2 Clock Timing 2.3.3 Reset Timing 2.3.4 Wakeup Time 2.3.5 NMI and IRQ Noise Filter 2.3.6 I/O Ports, POEG, GPT, AGTW, KINT, and ADC12 Trigger Timing 2.3.7 CAC Timing 2.3.8 SCI Timing 2.3.9 SPI Timing 2.3.10 I3C Timing 2.3.11 SSIE Timing 2.3.12 UARTA Timing 2.3.13 CLKOUT Timing 2.4 USB Characteristics 2.4.1 USBFS Timing 2.4.2 USBCC Characteristics 2.5 ADC12 Characteristics 2.6 TSN Characteristics 2.7 OSC Stop Detect Characteristics 2.8 POR and LVD Characteristics 2.9 Flash Memory Characteristics 2.9.1 Code Flash Memory Characteristics 2.9.2 Data Flash Memory Characteristics 2.10 Serial Wire Debug (SWD) Appendix 1. Port States in each Processing Mode Appendix 2. Package Dimensions Appendix 3. I/O Registers 3.1 Peripheral Base Addresses 3.2 Access Cycles Revision History General Precautions Notice